1 /*
2 * FreeRTOS Kernel <DEVELOPMENT BRANCH>
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 * Copyright 2024 Arm Limited and/or its affiliates
5 * <open-source-office@arm.com>
6 *
7 * SPDX-License-Identifier: MIT
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy of
10 * this software and associated documentation files (the "Software"), to deal in
11 * the Software without restriction, including without limitation the rights to
12 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
13 * the Software, and to permit persons to whom the Software is furnished to do so,
14 * subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in all
17 * copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
21 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
22 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
23 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
24 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * https://www.FreeRTOS.org
27 * https://github.com/FreeRTOS
28 *
29 */
30
31 /* Standard includes. */
32 #include <stdint.h>
33
34 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
35 * is defined correctly and privileged functions are placed in correct sections. */
36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
37
38 /* Portasm includes. */
39 #include "portasm.h"
40
41 /* System call numbers includes. */
42 #include "mpu_syscall_numbers.h"
43
44 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
45 * header files. */
46 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
47
48 #if ( configENABLE_MPU == 1 )
49
vRestoreContextOfFirstTask(void)50 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
51 {
52 __asm volatile
53 (
54 " .syntax unified \n"
55 " \n"
56 " program_mpu_first_task: \n"
57 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
58 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB. */
59 " \n"
60 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
61 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
62 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
63 " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
64 " str r2, [r1] \n" /* Disable MPU. */
65 " \n"
66 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
67 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
68 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
69 " str r1, [r2] \n" /* Program MAIR0. */
70 " \n"
71 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
72 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
73 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
74 " \n"
75 " movs r3, #4 \n" /* r3 = 4. */
76 " str r3, [r1] \n" /* Program RNR = 4. */
77 " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
78 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
79 " \n"
80 #if ( configTOTAL_MPU_REGIONS == 16 )
81 " movs r3, #8 \n" /* r3 = 8. */
82 " str r3, [r1] \n" /* Program RNR = 8. */
83 " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
84 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
85 " movs r3, #12 \n" /* r3 = 12. */
86 " str r3, [r1] \n" /* Program RNR = 12. */
87 " ldmia r0!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
88 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
89 #endif /* configTOTAL_MPU_REGIONS == 16 */
90 " \n"
91 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
92 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
93 " orr r2, #1 \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
94 " str r2, [r1] \n" /* Enable MPU. */
95 " dsb \n" /* Force memory writes before continuing. */
96 " \n"
97 " restore_context_first_task: \n"
98 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
99 " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
100 " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
101 " \n"
102 " restore_special_regs_first_task: \n"
103 #if ( configENABLE_PAC == 1 )
104 " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
105 " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
106 " msr PAC_KEY_P_1, r4 \n"
107 " msr PAC_KEY_P_2, r5 \n"
108 " msr PAC_KEY_P_3, r6 \n"
109 " clrm {r3-r6} \n" /* Clear r3-r6. */
110 #endif /* configENABLE_PAC */
111 " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
112 " msr psp, r3 \n"
113 " msr psplim, r4 \n"
114 " msr control, r5 \n"
115 " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
116 " str r0, [r4] \n" /* Restore xSecureContext. */
117 " \n"
118 " restore_general_regs_first_task: \n"
119 " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
120 " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
121 " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */
122 " \n"
123 " restore_context_done_first_task: \n"
124 " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
125 " mov r0, #0 \n"
126 " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
127 " bx lr \n"
128 );
129 }
130
131 #else /* configENABLE_MPU */
132
vRestoreContextOfFirstTask(void)133 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
134 {
135 __asm volatile
136 (
137 " .syntax unified \n"
138 " \n"
139 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
140 " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
141 " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
142 " \n"
143 #if ( configENABLE_PAC == 1 )
144 " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
145 " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
146 " msr PAC_KEY_P_2, r2 \n"
147 " msr PAC_KEY_P_1, r3 \n"
148 " msr PAC_KEY_P_0, r4 \n"
149 " clrm {r1-r4} \n" /* Clear r1-r4. */
150 #endif /* configENABLE_PAC */
151 " \n"
152 " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
153 " ldr r4, =xSecureContext \n"
154 " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
155 " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
156 " mrs r1, control \n" /* Obtain current control register value. */
157 " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
158 " msr control, r1 \n" /* Write back the new control register value. */
159 " adds r0, #32 \n" /* Discard everything up to r0. */
160 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
161 " isb \n"
162 " mov r0, #0 \n"
163 " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
164 " bx r3 \n" /* Finally, branch to EXC_RETURN. */
165 );
166 }
167
168 #endif /* configENABLE_MPU */
169 /*-----------------------------------------------------------*/
170
xIsPrivileged(void)171 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
172 {
173 __asm volatile
174 (
175 " .syntax unified \n"
176 " \n"
177 " mrs r0, control \n" /* r0 = CONTROL. */
178 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
179 " ite ne \n"
180 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
181 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
182 " bx lr \n" /* Return. */
183 ::: "r0", "memory"
184 );
185 }
186 /*-----------------------------------------------------------*/
187
vRaisePrivilege(void)188 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
189 {
190 __asm volatile
191 (
192 " .syntax unified \n"
193 " \n"
194 " mrs r0, control \n" /* Read the CONTROL register. */
195 " bic r0, #1 \n" /* Clear the bit 0. */
196 " msr control, r0 \n" /* Write back the new CONTROL value. */
197 " bx lr \n" /* Return to the caller. */
198 ::: "r0", "memory"
199 );
200 }
201 /*-----------------------------------------------------------*/
202
vResetPrivilege(void)203 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
204 {
205 __asm volatile
206 (
207 " .syntax unified \n"
208 " \n"
209 " mrs r0, control \n" /* r0 = CONTROL. */
210 " orr r0, #1 \n" /* r0 = r0 | 1. */
211 " msr control, r0 \n" /* CONTROL = r0. */
212 " bx lr \n" /* Return to the caller. */
213 ::: "r0", "memory"
214 );
215 }
216 /*-----------------------------------------------------------*/
217
vStartFirstTask(void)218 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
219 {
220 __asm volatile
221 (
222 " .syntax unified \n"
223 " \n"
224 " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
225 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
226 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
227 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
228 " cpsie i \n" /* Globally enable interrupts. */
229 " cpsie f \n"
230 " dsb \n"
231 " isb \n"
232 " svc %0 \n" /* System call to start the first task. */
233 " nop \n"
234 ::"i" ( portSVC_START_SCHEDULER ) : "memory"
235 );
236 }
237 /*-----------------------------------------------------------*/
238
ulSetInterruptMask(void)239 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
240 {
241 __asm volatile
242 (
243 " .syntax unified \n"
244 " \n"
245 " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
246 " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
247 " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
248 " dsb \n"
249 " isb \n"
250 " bx lr \n" /* Return. */
251 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
252 );
253 }
254 /*-----------------------------------------------------------*/
255
vClearInterruptMask(uint32_t ulMask)256 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
257 {
258 __asm volatile
259 (
260 " .syntax unified \n"
261 " \n"
262 " msr basepri, r0 \n" /* basepri = ulMask. */
263 " dsb \n"
264 " isb \n"
265 " bx lr \n" /* Return. */
266 ::: "memory"
267 );
268 }
269 /*-----------------------------------------------------------*/
270
271 #if ( configENABLE_MPU == 1 )
272
PendSV_Handler(void)273 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
274 {
275 __asm volatile
276 (
277 " .syntax unified \n"
278 " .extern SecureContext_SaveContext \n"
279 " .extern SecureContext_LoadContext \n"
280 " \n"
281 " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
282 " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
283 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
284 " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
285 " ldr r2, [r1] \n" /* r2 = Location in TCB where the context should be saved. */
286 " \n"
287 " cbz r0, save_ns_context \n" /* No secure context to save. */
288 " save_s_context: \n"
289 " push {r0-r2, lr} \n"
290 " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
291 " pop {r0-r2, lr} \n"
292 " \n"
293 " save_ns_context: \n"
294 " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
295 " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
296 " bmi save_special_regs \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
297 " \n"
298 " save_general_regs: \n"
299 " mrs r3, psp \n"
300 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
301 " add r3, r3, #0x20 \n" /* Move r3 to location where s0 is saved. */
302 " tst lr, #0x10 \n"
303 " ittt eq \n"
304 " vstmiaeq r2!, {s16-s31} \n" /* Store s16-s31. */
305 " vldmiaeq r3, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
306 " vstmiaeq r2!, {s0-s16} \n" /* Store hardware saved FP context. */
307 " sub r3, r3, #0x20 \n" /* Set r3 back to the location of hardware saved context. */
308 #endif /* configENABLE_FPU || configENABLE_MVE */
309 " stmia r2!, {r4-r11} \n" /* Store r4-r11. */
310 " ldmia r3, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
311 " stmia r2!, {r4-r11} \n" /* Store the hardware saved context. */
312 " \n"
313 " save_special_regs: \n"
314 " mrs r3, psp \n" /* r3 = PSP. */
315 " mrs r4, psplim \n" /* r4 = PSPLIM. */
316 " mrs r5, control \n" /* r5 = CONTROL. */
317 " stmia r2!, {r0, r3-r5, lr} \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
318 #if ( configENABLE_PAC == 1 )
319 " mrs r3, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
320 " mrs r4, PAC_KEY_P_1 \n"
321 " mrs r5, PAC_KEY_P_2 \n"
322 " mrs r6, PAC_KEY_P_3 \n"
323 " stmia r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the task's context. */
324 " clrm {r3-r6} \n" /* Clear r3-r6. */
325 #endif /* configENABLE_PAC */
326 " str r2, [r1] \n" /* Save the location from where the context should be restored as the first member of TCB. */
327 " \n"
328 " select_next_task: \n"
329 " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
330 " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
331 " dsb \n"
332 " isb \n"
333 " bl vTaskSwitchContext \n"
334 " mov r0, #0 \n" /* r0 = 0. */
335 " msr basepri, r0 \n" /* Enable interrupts. */
336 " \n"
337 " program_mpu: \n"
338 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
339 " ldr r0, [r3] \n" /* r0 = pxCurrentTCB.*/
340 " \n"
341 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
342 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
343 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
344 " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
345 " str r2, [r1] \n" /* Disable MPU. */
346 " \n"
347 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
348 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
349 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
350 " str r1, [r2] \n" /* Program MAIR0. */
351 " \n"
352 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
353 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
354 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
355 " \n"
356 " movs r3, #4 \n" /* r3 = 4. */
357 " str r3, [r1] \n" /* Program RNR = 4. */
358 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
359 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
360 " \n"
361 #if ( configTOTAL_MPU_REGIONS == 16 )
362 " movs r3, #8 \n" /* r3 = 8. */
363 " str r3, [r1] \n" /* Program RNR = 8. */
364 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
365 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
366 " movs r3, #12 \n" /* r3 = 12. */
367 " str r3, [r1] \n" /* Program RNR = 12. */
368 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
369 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
370 #endif /* configTOTAL_MPU_REGIONS == 16 */
371 " \n"
372 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
373 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
374 " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
375 " str r2, [r1] \n" /* Enable MPU. */
376 " dsb \n" /* Force memory writes before continuing. */
377 " \n"
378 " restore_context: \n"
379 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
380 " ldr r1, [r3] \n" /* r1 = pxCurrentTCB.*/
381 " ldr r2, [r1] \n" /* r2 = Location of saved context in TCB. */
382 " \n"
383 " restore_special_regs: \n"
384 #if ( configENABLE_PAC == 1 )
385 " ldmdb r2!, {r3-r6} \n" /* Read task's dedicated PAC key from the task's context. */
386 " msr PAC_KEY_P_0, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
387 " msr PAC_KEY_P_1, r4 \n"
388 " msr PAC_KEY_P_2, r5 \n"
389 " msr PAC_KEY_P_3, r6 \n"
390 " clrm {r3-r6} \n" /* Clear r3-r6. */
391 #endif /* configENABLE_PAC */
392 " ldmdb r2!, {r0, r3-r5, lr} \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
393 " msr psp, r3 \n"
394 " msr psplim, r4 \n"
395 " msr control, r5 \n"
396 " ldr r4, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
397 " str r0, [r4] \n" /* Restore xSecureContext. */
398 " cbz r0, restore_ns_context \n" /* No secure context to restore. */
399 " \n"
400 " restore_s_context: \n"
401 " push {r1-r3, lr} \n"
402 " bl SecureContext_LoadContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
403 " pop {r1-r3, lr} \n"
404 " \n"
405 " restore_ns_context: \n"
406 " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
407 " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
408 " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
409 " \n"
410 " restore_general_regs: \n"
411 " ldmdb r2!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
412 " stmia r3!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
413 " ldmdb r2!, {r4-r11} \n" /* r4-r11 restored. */
414 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
415 " tst lr, #0x10 \n"
416 " ittt eq \n"
417 " vldmdbeq r2!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
418 " vstmiaeq r3!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
419 " vldmdbeq r2!, {s16-s31} \n" /* Restore s16-s31. */
420 #endif /* configENABLE_FPU || configENABLE_MVE */
421 " \n"
422 " restore_context_done: \n"
423 " str r2, [r1] \n" /* Save the location where the context should be saved next as the first member of TCB. */
424 " bx lr \n"
425 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
426 );
427 }
428
429 #else /* configENABLE_MPU */
430
PendSV_Handler(void)431 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
432 {
433 __asm volatile
434 (
435 " .syntax unified \n"
436 " .extern SecureContext_SaveContext \n"
437 " .extern SecureContext_LoadContext \n"
438 " \n"
439 " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
440 " ldr r0, [r3] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
441 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
442 " ldr r1, [r3] \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
443 " mrs r2, psp \n" /* Read PSP in r2. */
444 " \n"
445 " cbz r0, save_ns_context \n" /* No secure context to save. */
446 " save_s_context: \n"
447 " push {r0-r2, lr} \n"
448 " bl SecureContext_SaveContext \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
449 " pop {r0-r2, lr} \n"
450 " \n"
451 " save_ns_context: \n"
452 " mov r3, lr \n" /* r3 = LR (EXC_RETURN). */
453 " lsls r3, r3, #25 \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
454 " bmi save_special_regs \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
455 " \n"
456 " save_general_regs: \n"
457 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
458 " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
459 " it eq \n"
460 " vstmdbeq r2!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
461 #endif /* configENABLE_FPU || configENABLE_MVE */
462 " stmdb r2!, {r4-r11} \n" /* Store the registers that are not saved automatically. */
463 " \n"
464 " save_special_regs: \n"
465 " mrs r3, psplim \n" /* r3 = PSPLIM. */
466 " stmdb r2!, {r0, r3, lr} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
467 #if ( configENABLE_PAC == 1 )
468 " mrs r3, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
469 " mrs r4, PAC_KEY_P_2 \n"
470 " mrs r5, PAC_KEY_P_1 \n"
471 " mrs r6, PAC_KEY_P_0 \n"
472 " stmdb r2!, {r3-r6} \n" /* Store the task's dedicated PAC key on the stack. */
473 " clrm {r3-r6} \n" /* Clear r3-r6. */
474 #endif /* configENABLE_PAC */
475 " \n"
476 " str r2, [r1] \n" /* Save the new top of stack in TCB. */
477 " \n"
478 " select_next_task: \n"
479 " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
480 " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
481 " dsb \n"
482 " isb \n"
483 " bl vTaskSwitchContext \n"
484 " mov r0, #0 \n" /* r0 = 0. */
485 " msr basepri, r0 \n" /* Enable interrupts. */
486 " \n"
487 " restore_context: \n"
488 " ldr r3, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
489 " ldr r1, [r3] \n" /* Read pxCurrentTCB. */
490 " ldr r2, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
491 " \n"
492 " restore_special_regs: \n"
493 #if ( configENABLE_PAC == 1 )
494 " ldmia r2!, {r3-r6} \n" /* Read task's dedicated PAC key from stack. */
495 " msr PAC_KEY_P_3, r3 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
496 " msr PAC_KEY_P_2, r4 \n"
497 " msr PAC_KEY_P_1, r5 \n"
498 " msr PAC_KEY_P_0, r6 \n"
499 " clrm {r3-r6} \n" /* Clear r3-r6. */
500 #endif /* configENABLE_PAC */
501 " ldmia r2!, {r0, r3, lr} \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
502 " msr psplim, r3 \n" /* Restore the PSPLIM register value for the task. */
503 " ldr r3, =xSecureContext \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
504 " str r0, [r3] \n" /* Restore the task's xSecureContext. */
505 " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
506 " \n"
507 " restore_s_context: \n"
508 " push {r1-r3, lr} \n"
509 " bl SecureContext_LoadContext \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
510 " pop {r1-r3, lr} \n"
511 " \n"
512 " restore_ns_context: \n"
513 " mov r0, lr \n" /* r0 = LR (EXC_RETURN). */
514 " lsls r0, r0, #25 \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
515 " bmi restore_context_done \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
516 " \n"
517 " restore_general_regs: \n"
518 " ldmia r2!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
519 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
520 " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
521 " it eq \n"
522 " vldmiaeq r2!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
523 #endif /* configENABLE_FPU || configENABLE_MVE */
524 " \n"
525 " restore_context_done: \n"
526 " msr psp, r2 \n" /* Remember the new top of stack for the task. */
527 " bx lr \n"
528 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
529 );
530 }
531
532 #endif /* configENABLE_MPU */
533 /*-----------------------------------------------------------*/
534
535 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
536
SVC_Handler(void)537 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
538 {
539 __asm volatile
540 (
541 ".syntax unified \n"
542 ".extern vPortSVCHandler_C \n"
543 ".extern vSystemCallEnter \n"
544 ".extern vSystemCallExit \n"
545 " \n"
546 "tst lr, #4 \n"
547 "ite eq \n"
548 "mrseq r0, msp \n"
549 "mrsne r0, psp \n"
550 " \n"
551 "ldr r1, [r0, #24] \n"
552 "ldrb r2, [r1, #-2] \n"
553 "cmp r2, %0 \n"
554 "blt syscall_enter \n"
555 "cmp r2, %1 \n"
556 "beq syscall_exit \n"
557 "b vPortSVCHandler_C \n"
558 " \n"
559 "syscall_enter: \n"
560 " mov r1, lr \n"
561 " b vSystemCallEnter \n"
562 " \n"
563 "syscall_exit: \n"
564 " mov r1, lr \n"
565 " b vSystemCallExit \n"
566 " \n"
567 : /* No outputs. */
568 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
569 : "r0", "r1", "r2", "memory"
570 );
571 }
572
573 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
574
SVC_Handler(void)575 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
576 {
577 __asm volatile
578 (
579 " .syntax unified \n"
580 " \n"
581 " tst lr, #4 \n"
582 " ite eq \n"
583 " mrseq r0, msp \n"
584 " mrsne r0, psp \n"
585 " ldr r1, =vPortSVCHandler_C \n"
586 " bx r1 \n"
587 );
588 }
589
590 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
591 /*-----------------------------------------------------------*/
592
vPortAllocateSecureContext(uint32_t ulSecureStackSize)593 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
594 {
595 __asm volatile
596 (
597 " .syntax unified \n"
598 " \n"
599 " svc %0 \n" /* Secure context is allocated in the supervisor call. */
600 " bx lr \n" /* Return. */
601 ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
602 );
603 }
604 /*-----------------------------------------------------------*/
605
vPortFreeSecureContext(uint32_t * pulTCB)606 void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
607 {
608 __asm volatile
609 (
610 " .syntax unified \n"
611 " \n"
612 " ldr r2, [r0] \n" /* The first item in the TCB is the top of the stack. */
613 " ldr r1, [r2] \n" /* The first item on the stack is the task's xSecureContext. */
614 " cmp r1, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
615 " it ne \n"
616 " svcne %0 \n" /* Secure context is freed in the supervisor call. */
617 " bx lr \n" /* Return. */
618 ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
619 );
620 }
621 /*-----------------------------------------------------------*/
622