1 /*
2 * FreeRTOS Kernel <DEVELOPMENT BRANCH>
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
26 *
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31
32 /* Scheduler includes. */
33 #include "FreeRTOS.h"
34 #include "task.h"
35
36 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
37 #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
38 #endif
39
40 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
41 #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
42 #endif
43
44 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
45 #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
46 #endif
47
48 #ifndef configSETUP_TICK_INTERRUPT
49 #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
50 #endif /* configSETUP_TICK_INTERRUPT */
51
52 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
53 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
54 #endif
55
56 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
57 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
58 #endif
59
60 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
61 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
62 #endif
63
64 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
65 /* Check the configuration. */
66 #if ( configMAX_PRIORITIES > 32 )
67 #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
68 #endif
69 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
70
71 /* In case security extensions are implemented. */
72 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
73 #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
74 #endif
75
76 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
77 * portmacro.h. */
78 #ifndef configCLEAR_TICK_INTERRUPT
79 #define configCLEAR_TICK_INTERRUPT()
80 #endif
81
82 /* A critical section is exited when the critical section nesting count reaches
83 * this value. */
84 #define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
85
86 /* In all GICs 255 can be written to the priority mask register to unmask all
87 * (but the lowest) interrupt priority. */
88 #define portUNMASK_VALUE ( 0xFFUL )
89
90 /* Tasks are not created with a floating point context, but can be given a
91 * floating point context after they have been created. A variable is stored as
92 * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
93 * does not have an FPU context, or any other value if the task does have an FPU
94 * context. */
95 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
96
97 /* Constants required to setup the initial task context. */
98 #define portSP_ELx ( ( StackType_t ) 0x01 )
99 #define portSP_EL0 ( ( StackType_t ) 0x00 )
100
101 #if defined( GUEST )
102 #define portEL1 ( ( StackType_t ) 0x04 )
103 #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
104 #else
105 #define portEL3 ( ( StackType_t ) 0x0c )
106 /* At the time of writing, the BSP only supports EL3. */
107 #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
108 #endif
109
110
111 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
112 * point is zero. */
113 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
114
115 /* Masks all bits in the APSR other than the mode bits. */
116 #define portAPSR_MODE_BITS_MASK ( 0x0C )
117
118 /* The I bit in the DAIF bits. */
119 #define portDAIF_I ( 0x80 )
120
121 /* Macro to unmask all interrupt priorities. */
122 #define portCLEAR_INTERRUPT_MASK() \
123 { \
124 portDISABLE_INTERRUPTS(); \
125 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
126 __asm volatile ( "DSB SY \n" \
127 "ISB SY \n" ); \
128 portENABLE_INTERRUPTS(); \
129 }
130
131 /* Hardware specifics used when sanity checking the configuration. */
132 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
133 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
134 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
135
136 /* The space on the stack required to hold the FPU registers.
137 * There are 32 128-bit registers.*/
138 #define portFPU_REGISTER_WORDS ( 32 * 2 )
139
140 /*-----------------------------------------------------------*/
141
142 /*
143 * Starts the first task executing. This function is necessarily written in
144 * assembly code so is implemented in portASM.s.
145 */
146 extern void vPortRestoreTaskContext( void );
147
148 /*-----------------------------------------------------------*/
149
150 /* A variable is used to keep track of the critical section nesting. This
151 * variable has to be stored as part of the task context and must be initialised to
152 * a non zero value to ensure interrupts don't inadvertently become unmasked before
153 * the scheduler starts. As it is stored as part of the task context it will
154 * automatically be set to 0 when the first task is started. */
155 volatile uint64_t ullCriticalNesting = 9999ULL;
156
157 /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
158 * then floating point context must be saved and restored for the task. */
159 uint64_t ullPortTaskHasFPUContext = pdFALSE;
160
161 /* Set to 1 to pend a context switch from an ISR. */
162 uint64_t ullPortYieldRequired = pdFALSE;
163
164 /* Counts the interrupt nesting depth. A context switch is only performed if
165 * if the nesting depth is 0. */
166 uint64_t ullPortInterruptNesting = 0;
167
168 /* Used in the ASM code. */
169 __attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
170 __attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
171 __attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
172 __attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
173
174 /*-----------------------------------------------------------*/
175
176 /*
177 * See header file for description.
178 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)179 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
180 TaskFunction_t pxCode,
181 void * pvParameters )
182 {
183 /* Setup the initial stack of the task. The stack is set exactly as
184 * expected by the portRESTORE_CONTEXT() macro. */
185
186 /* First all the general purpose registers. */
187 pxTopOfStack--;
188 *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
189 pxTopOfStack--;
190 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
191 pxTopOfStack--;
192 *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
193 pxTopOfStack--;
194 *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
195 pxTopOfStack--;
196 *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
197 pxTopOfStack--;
198 *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
199 pxTopOfStack--;
200 *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
201 pxTopOfStack--;
202 *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
203 pxTopOfStack--;
204 *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
205 pxTopOfStack--;
206 *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
207 pxTopOfStack--;
208 *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
209 pxTopOfStack--;
210 *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
211 pxTopOfStack--;
212 *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
213 pxTopOfStack--;
214 *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
215 pxTopOfStack--;
216 *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
217 pxTopOfStack--;
218 *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
219 pxTopOfStack--;
220 *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
221 pxTopOfStack--;
222 *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
223 pxTopOfStack--;
224 *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
225 pxTopOfStack--;
226 *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
227 pxTopOfStack--;
228 *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
229 pxTopOfStack--;
230 *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
231 pxTopOfStack--;
232 *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
233 pxTopOfStack--;
234 *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
235 pxTopOfStack--;
236 *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
237 pxTopOfStack--;
238 *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
239 pxTopOfStack--;
240 *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
241 pxTopOfStack--;
242 *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
243 pxTopOfStack--;
244 *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
245 pxTopOfStack--;
246 *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
247 pxTopOfStack--;
248 *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
249 pxTopOfStack--;
250 *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
251
252 pxTopOfStack--;
253 *pxTopOfStack = portINITIAL_PSTATE;
254
255 pxTopOfStack--;
256 *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
257
258 #if ( configUSE_TASK_FPU_SUPPORT == 1 )
259 {
260 /* The task will start with a critical nesting count of 0 as interrupts are
261 * enabled. */
262 pxTopOfStack--;
263 *pxTopOfStack = portNO_CRITICAL_NESTING;
264
265 /* The task will start without a floating point context. A task that
266 * uses the floating point hardware must call vPortTaskUsesFPU() before
267 * executing any floating point instructions. */
268 pxTopOfStack--;
269 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
270 }
271 #elif ( configUSE_TASK_FPU_SUPPORT == 2 )
272 {
273 /* The task will start with a floating point context. Leave enough
274 * space for the registers - and ensure they are initialised to 0. */
275 pxTopOfStack -= portFPU_REGISTER_WORDS;
276 memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
277
278 /* The task will start with a critical nesting count of 0 as interrupts are
279 * enabled. */
280 pxTopOfStack--;
281 *pxTopOfStack = portNO_CRITICAL_NESTING;
282
283 pxTopOfStack--;
284 *pxTopOfStack = pdTRUE;
285 ullPortTaskHasFPUContext = pdTRUE;
286 }
287 #else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
288 {
289 #error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
290 }
291 #endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
292
293 return pxTopOfStack;
294 }
295 /*-----------------------------------------------------------*/
296
xPortStartScheduler(void)297 BaseType_t xPortStartScheduler( void )
298 {
299 uint32_t ulAPSR;
300
301 #if ( configASSERT_DEFINED == 1 )
302 {
303 volatile uint8_t ucOriginalPriority;
304 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
305 volatile uint8_t ucMaxPriorityValue;
306
307 /* Determine how many priority bits are implemented in the GIC.
308 *
309 * Save the interrupt priority value that is about to be clobbered. */
310 ucOriginalPriority = *pucFirstUserPriorityRegister;
311
312 /* Determine the number of priority bits available. First write to
313 * all possible bits. */
314 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
315
316 /* Read the value back to see how many bits stuck. */
317 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
318
319 /* Shift to the least significant bits. */
320 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
321 {
322 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
323 }
324
325 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
326 * value. */
327
328 configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
329
330
331 /* Restore the clobbered interrupt priority register to its original
332 * value. */
333 *pucFirstUserPriorityRegister = ucOriginalPriority;
334 }
335 #endif /* configASSERT_DEFINED */
336
337
338 /* At the time of writing, the BSP only supports EL3. */
339 __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
340 ulAPSR &= portAPSR_MODE_BITS_MASK;
341
342 #if defined( GUEST )
343 #warning "Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH."
344 configASSERT( ulAPSR == portEL1 );
345
346 if( ulAPSR == portEL1 )
347 #else
348 configASSERT( ulAPSR == portEL3 );
349
350 if( ulAPSR == portEL3 )
351 #endif
352 {
353 /* Only continue if the binary point value is set to its lowest possible
354 * setting. See the comments in vPortValidateInterruptPriority() below for
355 * more information. */
356 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
357
358 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
359 {
360 /* Interrupts are turned off in the CPU itself to ensure a tick does
361 * not execute while the scheduler is being started. Interrupts are
362 * automatically turned back on in the CPU when the first task starts
363 * executing. */
364 portDISABLE_INTERRUPTS();
365
366 /* Start the timer that generates the tick ISR. */
367 configSETUP_TICK_INTERRUPT();
368
369 /* Start the first task executing. */
370 vPortRestoreTaskContext();
371 }
372 }
373
374 return 0;
375 }
376 /*-----------------------------------------------------------*/
377
vPortEndScheduler(void)378 void vPortEndScheduler( void )
379 {
380 /* Not implemented in ports where there is nothing to return to.
381 * Artificially force an assert. */
382 configASSERT( ullCriticalNesting == 1000ULL );
383 }
384 /*-----------------------------------------------------------*/
385
vPortEnterCritical(void)386 void vPortEnterCritical( void )
387 {
388 /* Mask interrupts up to the max syscall interrupt priority. */
389 uxPortSetInterruptMask();
390
391 /* Now interrupts are disabled ullCriticalNesting can be accessed
392 * directly. Increment ullCriticalNesting to keep a count of how many times
393 * portENTER_CRITICAL() has been called. */
394 ullCriticalNesting++;
395
396 /* This is not the interrupt safe version of the enter critical function so
397 * assert() if it is being called from an interrupt context. Only API
398 * functions that end in "FromISR" can be used in an interrupt. Only assert if
399 * the critical nesting count is 1 to protect against recursive calls if the
400 * assert function also uses a critical section. */
401 if( ullCriticalNesting == 1ULL )
402 {
403 configASSERT( ullPortInterruptNesting == 0 );
404 }
405 }
406 /*-----------------------------------------------------------*/
407
vPortExitCritical(void)408 void vPortExitCritical( void )
409 {
410 if( ullCriticalNesting > portNO_CRITICAL_NESTING )
411 {
412 /* Decrement the nesting count as the critical section is being
413 * exited. */
414 ullCriticalNesting--;
415
416 /* If the nesting level has reached zero then all interrupt
417 * priorities must be re-enabled. */
418 if( ullCriticalNesting == portNO_CRITICAL_NESTING )
419 {
420 /* Critical nesting has reached zero so all interrupt priorities
421 * should be unmasked. */
422 portCLEAR_INTERRUPT_MASK();
423 }
424 }
425 }
426 /*-----------------------------------------------------------*/
427
FreeRTOS_Tick_Handler(void)428 void FreeRTOS_Tick_Handler( void )
429 {
430 /* Must be the lowest possible priority. */
431 #if !defined( QEMU )
432 {
433 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
434 }
435 #endif
436
437 /* Interrupts should not be enabled before this point. */
438 #if ( configASSERT_DEFINED == 1 )
439 {
440 uint32_t ulMaskBits;
441
442 __asm volatile ( "mrs %0, daif" : "=r" ( ulMaskBits )::"memory" );
443 configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
444 }
445 #endif /* configASSERT_DEFINED */
446
447 /* Set interrupt mask before altering scheduler structures. The tick
448 * handler runs at the lowest priority, so interrupts cannot already be masked,
449 * so there is no need to save and restore the current mask value. It is
450 * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
451 * updated. */
452 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
453 __asm volatile ( "dsb sy \n"
454 "isb sy \n" ::: "memory" );
455
456 /* Ok to enable interrupts after the interrupt source has been cleared. */
457 configCLEAR_TICK_INTERRUPT();
458 portENABLE_INTERRUPTS();
459
460 /* Increment the RTOS tick. */
461 if( xTaskIncrementTick() != pdFALSE )
462 {
463 ullPortYieldRequired = pdTRUE;
464 }
465
466 /* Ensure all interrupt priorities are active again. */
467 portCLEAR_INTERRUPT_MASK();
468 }
469 /*-----------------------------------------------------------*/
470
471 #if ( configUSE_TASK_FPU_SUPPORT != 2 )
472
vPortTaskUsesFPU(void)473 void vPortTaskUsesFPU( void )
474 {
475 /* A task is registering the fact that it needs an FPU context. Set the
476 * FPU flag (which is saved as part of the task context). */
477 ullPortTaskHasFPUContext = pdTRUE;
478
479 /* Consider initialising the FPSR here - but probably not necessary in
480 * AArch64. */
481 }
482
483 #endif /* configUSE_TASK_FPU_SUPPORT */
484 /*-----------------------------------------------------------*/
485
vPortClearInterruptMask(UBaseType_t uxNewMaskValue)486 void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
487 {
488 if( uxNewMaskValue == pdFALSE )
489 {
490 portCLEAR_INTERRUPT_MASK();
491 }
492 }
493 /*-----------------------------------------------------------*/
494
uxPortSetInterruptMask(void)495 UBaseType_t uxPortSetInterruptMask( void )
496 {
497 uint32_t ulReturn;
498
499 /* Interrupt in the CPU must be turned off while the ICCPMR is being
500 * updated. */
501 portDISABLE_INTERRUPTS();
502
503 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
504 {
505 /* Interrupts were already masked. */
506 ulReturn = pdTRUE;
507 }
508 else
509 {
510 ulReturn = pdFALSE;
511 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
512 __asm volatile ( "dsb sy \n"
513 "isb sy \n" ::: "memory" );
514 }
515
516 portENABLE_INTERRUPTS();
517
518 return ulReturn;
519 }
520 /*-----------------------------------------------------------*/
521
522 #if ( configASSERT_DEFINED == 1 )
523
vPortValidateInterruptPriority(void)524 void vPortValidateInterruptPriority( void )
525 {
526 /* The following assertion will fail if a service routine (ISR) for
527 * an interrupt that has been assigned a priority above
528 * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
529 * function. ISR safe FreeRTOS API functions must *only* be called
530 * from interrupts that have been assigned a priority at or below
531 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
532 *
533 * Numerically low interrupt priority numbers represent logically high
534 * interrupt priorities, therefore the priority of the interrupt must
535 * be set to a value equal to or numerically *higher* than
536 * configMAX_SYSCALL_INTERRUPT_PRIORITY.
537 *
538 * FreeRTOS maintains separate thread and ISR API functions to ensure
539 * interrupt entry is as fast and simple as possible. */
540 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
541
542 /* Priority grouping: The interrupt controller (GIC) allows the bits
543 * that define each interrupt's priority to be split between bits that
544 * define the interrupt's pre-emption priority bits and bits that define
545 * the interrupt's sub-priority. For simplicity all bits must be defined
546 * to be pre-emption priority bits. The following assertion will fail if
547 * this is not the case (if some bits represent a sub-priority).
548 *
549 * The priority grouping is configured by the GIC's binary point register
550 * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
551 * possible value (which may be above 0). */
552 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
553 }
554
555 #endif /* configASSERT_DEFINED */
556 /*-----------------------------------------------------------*/
557