1 /*
2 * FreeRTOS Kernel <DEVELOPMENT BRANCH>
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 * Copyright 2024 Arm Limited and/or its affiliates
5 * <open-source-office@arm.com>
6 *
7 * SPDX-License-Identifier: MIT
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy of
10 * this software and associated documentation files (the "Software"), to deal in
11 * the Software without restriction, including without limitation the rights to
12 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
13 * the Software, and to permit persons to whom the Software is furnished to do so,
14 * subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in all
17 * copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
21 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
22 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
23 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
24 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * https://www.FreeRTOS.org
27 * https://github.com/FreeRTOS
28 *
29 */
30
31 /* Standard includes. */
32 #include <stdint.h>
33
34 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
35 * is defined correctly and privileged functions are placed in correct sections. */
36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
37
38 /* Portasm includes. */
39 #include "portasm.h"
40
41 /* System call numbers includes. */
42 #include "mpu_syscall_numbers.h"
43
44 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
45 * header files. */
46 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
47
48 #if ( configENABLE_MPU == 1 )
49
vRestoreContextOfFirstTask(void)50 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
51 {
52 __asm volatile
53 (
54 " .syntax unified \n"
55 " \n"
56 " program_mpu_first_task: \n"
57 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
58 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
59 " \n"
60 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
61 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
62 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
63 " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
64 " str r2, [r1] \n" /* Disable MPU. */
65 " \n"
66 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
67 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
68 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
69 " str r1, [r2] \n" /* Program MAIR0. */
70 " \n"
71 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
72 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
73 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
74 " \n"
75 " movs r3, #4 \n" /* r3 = 4. */
76 " str r3, [r1] \n" /* Program RNR = 4. */
77 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
78 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
79 " \n"
80 #if ( configTOTAL_MPU_REGIONS == 16 )
81 " movs r3, #8 \n" /* r3 = 8. */
82 " str r3, [r1] \n" /* Program RNR = 8. */
83 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
84 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
85 " movs r3, #12 \n" /* r3 = 12. */
86 " str r3, [r1] \n" /* Program RNR = 12. */
87 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
88 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
89 #endif /* configTOTAL_MPU_REGIONS == 16 */
90 " \n"
91 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
92 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
93 " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
94 " str r2, [r1] \n" /* Enable MPU. */
95 " dsb \n" /* Force memory writes before continuing. */
96 " \n"
97 " restore_context_first_task: \n"
98 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
99 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
100 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
101 " \n"
102 " restore_special_regs_first_task: \n"
103 #if ( configENABLE_PAC == 1 )
104 " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
105 " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
106 " msr PAC_KEY_P_1, r3 \n"
107 " msr PAC_KEY_P_2, r4 \n"
108 " msr PAC_KEY_P_3, r5 \n"
109 " clrm {r2-r5} \n" /* Clear r2-r5. */
110 #endif /* configENABLE_PAC */
111 " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
112 " msr psp, r2 \n"
113 " msr psplim, r3 \n"
114 " msr control, r4 \n"
115 " \n"
116 " restore_general_regs_first_task: \n"
117 " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
118 " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
119 " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */
120 " \n"
121 " restore_context_done_first_task: \n"
122 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
123 " mov r0, #0 \n"
124 " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
125 " bx lr \n"
126 );
127 }
128
129 #else /* configENABLE_MPU */
130
vRestoreContextOfFirstTask(void)131 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
132 {
133 __asm volatile
134 (
135 " .syntax unified \n"
136 " \n"
137 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
138 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
139 " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
140 " \n"
141 #if ( configENABLE_PAC == 1 )
142 " ldmia r0!, {r1-r4} \n" /* Read task's dedicated PAC key from stack. */
143 " msr PAC_KEY_P_3, r1 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
144 " msr PAC_KEY_P_2, r2 \n"
145 " msr PAC_KEY_P_1, r3 \n"
146 " msr PAC_KEY_P_0, r4 \n"
147 " clrm {r1-r4} \n" /* Clear r1-r4. */
148 #endif /* configENABLE_PAC */
149 " \n"
150 " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
151 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
152 " mrs r1, control \n" /* Obtain current control register value. */
153 " orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
154 " msr control, r1 \n" /* Write back the new control register value. */
155 " adds r0, #32 \n" /* Discard everything up to r0. */
156 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
157 " isb \n"
158 " mov r0, #0 \n"
159 " msr basepri, r0 \n" /* Ensure that interrupts are enabled when the first task starts. */
160 " bx r2 \n" /* Finally, branch to EXC_RETURN. */
161 );
162 }
163
164 #endif /* configENABLE_MPU */
165 /*-----------------------------------------------------------*/
166
xIsPrivileged(void)167 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
168 {
169 __asm volatile
170 (
171 " .syntax unified \n"
172 " \n"
173 " mrs r0, control \n" /* r0 = CONTROL. */
174 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
175 " ite ne \n"
176 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
177 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
178 " bx lr \n" /* Return. */
179 ::: "r0", "memory"
180 );
181 }
182 /*-----------------------------------------------------------*/
183
vRaisePrivilege(void)184 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
185 {
186 __asm volatile
187 (
188 " .syntax unified \n"
189 " \n"
190 " mrs r0, control \n" /* Read the CONTROL register. */
191 " bic r0, #1 \n" /* Clear the bit 0. */
192 " msr control, r0 \n" /* Write back the new CONTROL value. */
193 " bx lr \n" /* Return to the caller. */
194 ::: "r0", "memory"
195 );
196 }
197 /*-----------------------------------------------------------*/
198
vResetPrivilege(void)199 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
200 {
201 __asm volatile
202 (
203 " .syntax unified \n"
204 " \n"
205 " mrs r0, control \n" /* r0 = CONTROL. */
206 " orr r0, #1 \n" /* r0 = r0 | 1. */
207 " msr control, r0 \n" /* CONTROL = r0. */
208 " bx lr \n" /* Return to the caller. */
209 ::: "r0", "memory"
210 );
211 }
212 /*-----------------------------------------------------------*/
213
vStartFirstTask(void)214 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
215 {
216 __asm volatile
217 (
218 " .syntax unified \n"
219 " \n"
220 " ldr r0, =0xe000ed08 \n" /* Use the NVIC offset register to locate the stack. */
221 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
222 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
223 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
224 " cpsie i \n" /* Globally enable interrupts. */
225 " cpsie f \n"
226 " dsb \n"
227 " isb \n"
228 " svc %0 \n" /* System call to start the first task. */
229 " nop \n"
230 ::"i" ( portSVC_START_SCHEDULER ) : "memory"
231 );
232 }
233 /*-----------------------------------------------------------*/
234
ulSetInterruptMask(void)235 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
236 {
237 __asm volatile
238 (
239 " .syntax unified \n"
240 " \n"
241 " mrs r0, basepri \n" /* r0 = basepri. Return original basepri value. */
242 " mov r1, %0 \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
243 " msr basepri, r1 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
244 " dsb \n"
245 " isb \n"
246 " bx lr \n" /* Return. */
247 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
248 );
249 }
250 /*-----------------------------------------------------------*/
251
vClearInterruptMask(uint32_t ulMask)252 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
253 {
254 __asm volatile
255 (
256 " .syntax unified \n"
257 " \n"
258 " msr basepri, r0 \n" /* basepri = ulMask. */
259 " dsb \n"
260 " isb \n"
261 " bx lr \n" /* Return. */
262 ::: "memory"
263 );
264 }
265 /*-----------------------------------------------------------*/
266
267 #if ( configENABLE_MPU == 1 )
268
PendSV_Handler(void)269 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
270 {
271 __asm volatile
272 (
273 " .syntax unified \n"
274 " \n"
275 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
276 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
277 " ldr r1, [r0] \n" /* r1 = Location in TCB where the context should be saved. */
278 " mrs r2, psp \n" /* r2 = PSP. */
279 " \n"
280 " save_general_regs: \n"
281 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
282 " add r2, r2, #0x20 \n" /* Move r2 to location where s0 is saved. */
283 " tst lr, #0x10 \n"
284 " ittt eq \n"
285 " vstmiaeq r1!, {s16-s31} \n" /* Store s16-s31. */
286 " vldmiaeq r2, {s0-s16} \n" /* Copy hardware saved FP context into s0-s16. */
287 " vstmiaeq r1!, {s0-s16} \n" /* Store hardware saved FP context. */
288 " sub r2, r2, #0x20 \n" /* Set r2 back to the location of hardware saved context. */
289 #endif /* configENABLE_FPU || configENABLE_MVE */
290 " stmia r1!, {r4-r11} \n" /* Store r4-r11. */
291 " ldmia r2, {r4-r11} \n" /* Copy the hardware saved context into r4-r11. */
292 " stmia r1!, {r4-r11} \n" /* Store the hardware saved context. */
293 " \n"
294 " save_special_regs: \n"
295 " mrs r3, psplim \n" /* r3 = PSPLIM. */
296 " mrs r4, control \n" /* r4 = CONTROL. */
297 " stmia r1!, {r2-r4, lr} \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
298 #if ( configENABLE_PAC == 1 )
299 " mrs r2, PAC_KEY_P_0 \n" /* Read task's dedicated PAC key from the PAC key registers. */
300 " mrs r3, PAC_KEY_P_1 \n"
301 " mrs r4, PAC_KEY_P_2 \n"
302 " mrs r5, PAC_KEY_P_3 \n"
303 " stmia r1!, {r2-r5} \n" /* Store the task's dedicated PAC key on the task's context. */
304 " clrm {r2-r5} \n" /* Clear r2-r5. */
305 #endif /* configENABLE_PAC */
306 " str r1, [r0] \n" /* Save the location from where the context should be restored as the first member of TCB. */
307 " \n"
308 " select_next_task: \n"
309 " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
310 " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
311 " dsb \n"
312 " isb \n"
313 " bl vTaskSwitchContext \n"
314 " mov r0, #0 \n" /* r0 = 0. */
315 " msr basepri, r0 \n" /* Enable interrupts. */
316 " \n"
317 " program_mpu: \n"
318 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
319 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB. */
320 " \n"
321 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
322 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
323 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
324 " bic r2, #1 \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
325 " str r2, [r1] \n" /* Disable MPU. */
326 " \n"
327 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
328 " ldr r1, [r0] \n" /* r1 = *r0 i.e. r1 = MAIR0. */
329 " ldr r2, =0xe000edc0 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
330 " str r1, [r2] \n" /* Program MAIR0. */
331 " \n"
332 " adds r0, #4 \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
333 " ldr r1, =0xe000ed98 \n" /* r1 = 0xe000ed98 [Location of RNR]. */
334 " ldr r2, =0xe000ed9c \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
335 " \n"
336 " movs r3, #4 \n" /* r3 = 4. */
337 " str r3, [r1] \n" /* Program RNR = 4. */
338 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
339 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
340 " \n"
341 #if ( configTOTAL_MPU_REGIONS == 16 )
342 " movs r3, #8 \n" /* r3 = 8. */
343 " str r3, [r1] \n" /* Program RNR = 8. */
344 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
345 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
346 " movs r3, #12 \n" /* r3 = 12. */
347 " str r3, [r1] \n" /* Program RNR = 12. */
348 " ldmia r0!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
349 " stmia r2, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
350 #endif /* configTOTAL_MPU_REGIONS == 16 */
351 " \n"
352 " ldr r1, =0xe000ed94 \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
353 " ldr r2, [r1] \n" /* Read the value of MPU_CTRL. */
354 " orr r2, #1 \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
355 " str r2, [r1] \n" /* Enable MPU. */
356 " dsb \n" /* Force memory writes before continuing. */
357 " \n"
358 " restore_context: \n"
359 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
360 " ldr r0, [r2] \n" /* r0 = pxCurrentTCB.*/
361 " ldr r1, [r0] \n" /* r1 = Location of saved context in TCB. */
362 " \n"
363 " restore_special_regs: \n"
364 #if ( configENABLE_PAC == 1 )
365 " ldmdb r1!, {r2-r5} \n" /* Read task's dedicated PAC key from the task's context. */
366 " msr PAC_KEY_P_0, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
367 " msr PAC_KEY_P_1, r3 \n"
368 " msr PAC_KEY_P_2, r4 \n"
369 " msr PAC_KEY_P_3, r5 \n"
370 " clrm {r2-r5} \n" /* Clear r2-r5. */
371 #endif /* configENABLE_PAC */
372 " ldmdb r1!, {r2-r4, lr} \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
373 " msr psp, r2 \n"
374 " msr psplim, r3 \n"
375 " msr control, r4 \n"
376 " \n"
377 " restore_general_regs: \n"
378 " ldmdb r1!, {r4-r11} \n" /* r4-r11 contain hardware saved context. */
379 " stmia r2!, {r4-r11} \n" /* Copy the hardware saved context on the task stack. */
380 " ldmdb r1!, {r4-r11} \n" /* r4-r11 restored. */
381 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
382 " tst lr, #0x10 \n"
383 " ittt eq \n"
384 " vldmdbeq r1!, {s0-s16} \n" /* s0-s16 contain hardware saved FP context. */
385 " vstmiaeq r2!, {s0-s16} \n" /* Copy hardware saved FP context on the task stack. */
386 " vldmdbeq r1!, {s16-s31} \n" /* Restore s16-s31. */
387 #endif /* configENABLE_FPU || configENABLE_MVE */
388 " \n"
389 " restore_context_done: \n"
390 " str r1, [r0] \n" /* Save the location where the context should be saved next as the first member of TCB. */
391 " bx lr \n"
392 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
393 );
394 }
395
396 #else /* configENABLE_MPU */
397
PendSV_Handler(void)398 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
399 {
400 __asm volatile
401 (
402 " .syntax unified \n"
403 " \n"
404 " mrs r0, psp \n" /* Read PSP in r0. */
405 " \n"
406 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
407 " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
408 " it eq \n"
409 " vstmdbeq r0!, {s16-s31} \n" /* Store the additional FP context registers which are not saved automatically. */
410 #endif /* configENABLE_FPU || configENABLE_MVE */
411 " \n"
412 " mrs r2, psplim \n" /* r2 = PSPLIM. */
413 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
414 " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
415 " \n"
416 #if ( configENABLE_PAC == 1 )
417 " mrs r1, PAC_KEY_P_3 \n" /* Read task's dedicated PAC key from the PAC key registers. */
418 " mrs r2, PAC_KEY_P_2 \n"
419 " mrs r3, PAC_KEY_P_1 \n"
420 " mrs r4, PAC_KEY_P_0 \n"
421 " stmdb r0!, {r1-r4} \n" /* Store the task's dedicated PAC key on the stack. */
422 " clrm {r1-r4} \n" /* Clear r1-r4. */
423 #endif /* configENABLE_PAC */
424 " \n"
425 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
426 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
427 " str r0, [r1] \n" /* Save the new top of stack in TCB. */
428 " \n"
429 " mov r0, %0 \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
430 " msr basepri, r0 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
431 " dsb \n"
432 " isb \n"
433 " bl vTaskSwitchContext \n"
434 " mov r0, #0 \n" /* r0 = 0. */
435 " msr basepri, r0 \n" /* Enable interrupts. */
436 " \n"
437 " ldr r2, =pxCurrentTCB \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
438 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
439 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
440 " \n"
441 #if ( configENABLE_PAC == 1 )
442 " ldmia r0!, {r2-r5} \n" /* Read task's dedicated PAC key from stack. */
443 " msr PAC_KEY_P_3, r2 \n" /* Write the task's dedicated PAC key to the PAC key registers. */
444 " msr PAC_KEY_P_2, r3 \n"
445 " msr PAC_KEY_P_1, r4 \n"
446 " msr PAC_KEY_P_0, r5 \n"
447 " clrm {r2-r5} \n" /* Clear r2-r5. */
448 #endif /* configENABLE_PAC */
449 " \n"
450 " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
451 " \n"
452 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
453 " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
454 " it eq \n"
455 " vldmiaeq r0!, {s16-s31} \n" /* Restore the additional FP context registers which are not restored automatically. */
456 #endif /* configENABLE_FPU || configENABLE_MVE */
457 " \n"
458 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
459 " msr psp, r0 \n" /* Remember the new top of stack for the task. */
460 " bx r3 \n"
461 ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
462 );
463 }
464
465 #endif /* configENABLE_MPU */
466 /*-----------------------------------------------------------*/
467
468 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
469
SVC_Handler(void)470 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
471 {
472 __asm volatile
473 (
474 ".syntax unified \n"
475 ".extern vPortSVCHandler_C \n"
476 ".extern vSystemCallEnter \n"
477 ".extern vSystemCallExit \n"
478 " \n"
479 "tst lr, #4 \n"
480 "ite eq \n"
481 "mrseq r0, msp \n"
482 "mrsne r0, psp \n"
483 " \n"
484 "ldr r1, [r0, #24] \n"
485 "ldrb r2, [r1, #-2] \n"
486 "cmp r2, %0 \n"
487 "blt syscall_enter \n"
488 "cmp r2, %1 \n"
489 "beq syscall_exit \n"
490 "b vPortSVCHandler_C \n"
491 " \n"
492 "syscall_enter: \n"
493 " mov r1, lr \n"
494 " b vSystemCallEnter \n"
495 " \n"
496 "syscall_exit: \n"
497 " mov r1, lr \n"
498 " b vSystemCallExit \n"
499 " \n"
500 : /* No outputs. */
501 : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
502 : "r0", "r1", "r2", "memory"
503 );
504 }
505
506 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
507
SVC_Handler(void)508 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
509 {
510 __asm volatile
511 (
512 " .syntax unified \n"
513 " \n"
514 " tst lr, #4 \n"
515 " ite eq \n"
516 " mrseq r0, msp \n"
517 " mrsne r0, psp \n"
518 " ldr r1, =vPortSVCHandler_C \n"
519 " bx r1 \n"
520 );
521 }
522
523 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
524 /*-----------------------------------------------------------*/
525