Lines Matching refs:dev
106 static void pci_lintr_route(struct pci_vdev *dev);
107 static void pci_lintr_update(struct pci_vdev *dev);
196 CFGWRITE(struct pci_vdev *dev, int coff, uint32_t val, int bytes) in CFGWRITE() argument
199 pci_set_cfgdata8(dev, coff, val); in CFGWRITE()
201 pci_set_cfgdata16(dev, coff, val); in CFGWRITE()
203 pci_set_cfgdata32(dev, coff, val); in CFGWRITE()
207 CFGREAD(struct pci_vdev *dev, int coff, int bytes) in CFGREAD() argument
210 return pci_get_cfgdata8(dev, coff); in CFGREAD()
212 return pci_get_cfgdata16(dev, coff); in CFGREAD()
214 return pci_get_cfgdata32(dev, coff); in CFGREAD()
218 is_pt_pci(struct pci_vdev *dev) in is_pt_pci() argument
220 if (dev == NULL || strncmp(dev->dev_ops->class_name, "passthru",8)) in is_pt_pci()
252 parse_bdf(char *s, int *bus, int *dev, int *func, int base) in parse_bdf() argument
260 dev ? *dev = 0 : 0; in parse_bdf()
273 if (s_dev && dev) in parse_bdf()
274 ret |= dm_strtoi(s_dev, &s_dev, base, dev); in parse_bdf()
377 pci_valid_pba_offset(struct pci_vdev *dev, uint64_t offset) in pci_valid_pba_offset() argument
379 if (offset < dev->msix.pba_offset) in pci_valid_pba_offset()
382 if (offset >= dev->msix.pba_offset + dev->msix.pba_size) in pci_valid_pba_offset()
389 pci_emul_msix_twrite(struct pci_vdev *dev, uint64_t offset, int size, in pci_emul_msix_twrite() argument
404 if (tab_index >= dev->msix.table_count) in pci_emul_msix_twrite()
413 dest = (char *)(dev->msix.table + tab_index); in pci_emul_msix_twrite()
425 pci_emul_msix_tread(struct pci_vdev *dev, uint64_t offset, int size) in pci_emul_msix_tread() argument
448 if (tab_index < dev->msix.table_count) { in pci_emul_msix_tread()
450 dest = (char *)(dev->msix.table + tab_index); in pci_emul_msix_tread()
459 } else if (pci_valid_pba_offset(dev, offset)) { in pci_emul_msix_tread()
468 pci_msix_table_bar(struct pci_vdev *dev) in pci_msix_table_bar() argument
470 if (dev->msix.table != NULL) in pci_msix_table_bar()
471 return dev->msix.table_bar; in pci_msix_table_bar()
477 pci_msix_pba_bar(struct pci_vdev *dev) in pci_msix_pba_bar() argument
479 if (dev->msix.table != NULL) in pci_msix_pba_bar()
480 return dev->msix.pba_bar; in pci_msix_pba_bar()
613 modify_bar_registration(struct pci_vdev *dev, int idx, int registration) in modify_bar_registration() argument
619 if (is_pt_pci(dev)) { in modify_bar_registration()
620 pr_dbg("%s: bypass for pci-passthru %x:%x.%x\n", __func__, dev->bus, dev->slot, dev->func); in modify_bar_registration()
624 switch (dev->bar[idx].type) { in modify_bar_registration()
627 iop.name = dev->name; in modify_bar_registration()
628 iop.port = dev->bar[idx].addr; in modify_bar_registration()
629 iop.size = dev->bar[idx].size; in modify_bar_registration()
633 iop.arg = dev; in modify_bar_registration()
641 mr.name = dev->name; in modify_bar_registration()
642 mr.base = dev->bar[idx].addr; in modify_bar_registration()
643 mr.size = dev->bar[idx].size; in modify_bar_registration()
647 mr.arg1 = dev; in modify_bar_registration()
662 unregister_bar(struct pci_vdev *dev, int idx) in unregister_bar() argument
664 modify_bar_registration(dev, idx, 0); in unregister_bar()
668 register_bar(struct pci_vdev *dev, int idx) in register_bar() argument
670 return modify_bar_registration(dev, idx, 1); in register_bar()
675 porten(struct pci_vdev *dev) in porten() argument
679 cmd = pci_get_cfgdata16(dev, PCIR_COMMAND); in porten()
686 memen(struct pci_vdev *dev) in memen() argument
690 cmd = pci_get_cfgdata16(dev, PCIR_COMMAND); in memen()
702 update_bar_address(struct vmctx *ctx, struct pci_vdev *dev, uint64_t addr, in update_bar_address() argument
708 if (dev->bar[idx].type == PCIBAR_IO) in update_bar_address()
709 decode = porten(dev); in update_bar_address()
711 decode = memen(dev); in update_bar_address()
715 unregister_bar(dev, idx); in update_bar_address()
733 dev->bar[idx].addr = addr; in update_bar_address()
736 dev->bar[idx].addr &= ~0xffffffffUL; in update_bar_address()
737 dev->bar[idx].addr |= addr; in update_bar_address()
740 dev->bar[idx].addr &= 0xffffffff; in update_bar_address()
741 dev->bar[idx].addr |= addr; in update_bar_address()
749 register_bar(dev, idx); in update_bar_address()
941 pci_emul_add_capability(struct pci_vdev *dev, u_char *capdata, int caplen) in pci_emul_add_capability() argument
948 sts = pci_get_cfgdata16(dev, PCIR_STATUS); in pci_emul_add_capability()
952 capoff = dev->capend + 1; in pci_emul_add_capability()
960 pci_set_cfgdata8(dev, PCIR_CAP_PTR, capoff); in pci_emul_add_capability()
961 pci_set_cfgdata16(dev, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); in pci_emul_add_capability()
963 pci_set_cfgdata8(dev, dev->prevcap + 1, capoff); in pci_emul_add_capability()
967 pci_set_cfgdata8(dev, capoff + i, capdata[i]); in pci_emul_add_capability()
970 pci_set_cfgdata8(dev, capoff + 1, 0); in pci_emul_add_capability()
972 dev->prevcap = capoff; in pci_emul_add_capability()
973 dev->capend = capoff + reallen - 1; in pci_emul_add_capability()
986 pci_emul_find_capability(struct pci_vdev *dev, uint8_t capid, int *p_capoff) in pci_emul_find_capability() argument
991 sts = pci_get_cfgdata16(dev, PCIR_STATUS); in pci_emul_find_capability()
999 coff = pci_get_cfgdata8(dev, PCIR_CAP_PTR); in pci_emul_find_capability()
1000 else if (*p_capoff >= CAP_START_OFFSET && *p_capoff <= dev->prevcap) in pci_emul_find_capability()
1001 coff = pci_get_cfgdata8(dev, *p_capoff + 1); in pci_emul_find_capability()
1005 while (coff >= CAP_START_OFFSET && coff <= dev->prevcap) { in pci_emul_find_capability()
1006 if (pci_get_cfgdata8(dev, coff) == capid) { in pci_emul_find_capability()
1010 coff = pci_get_cfgdata8(dev, coff + 1); in pci_emul_find_capability()
1093 pci_access_msi(struct pci_vdev *dev, int msi_cap, uint32_t *val, bool is_write) in pci_access_msi() argument
1102 rc = pci_emul_find_capability(dev, PCIY_MSI, &offset); in pci_access_msi()
1106 msgctrl = pci_get_cfgdata16(dev, offset + PCIR_MSI_CTRL); in pci_access_msi()
1113 pci_set_cfgdata32(dev, offset, *val); in pci_access_msi()
1115 *val = pci_get_cfgdata32(dev, offset); in pci_access_msi()
1120 pci_is_msi_masked(struct pci_vdev *dev, uint32_t index) in pci_is_msi_masked() argument
1125 rc = pci_access_msi(dev, PCIR_MSI_MASK, &val, false); in pci_is_msi_masked()
1132 pci_is_msi_pending(struct pci_vdev *dev, uint32_t index) in pci_is_msi_pending() argument
1137 rc = pci_access_msi(dev, PCIR_MSI_PENDING, &val, false); in pci_is_msi_pending()
1144 pci_set_msi_pending(struct pci_vdev *dev, uint32_t index, bool set) in pci_set_msi_pending() argument
1149 rc = pci_access_msi(dev, PCIR_MSI_PENDING, in pci_set_msi_pending()
1160 pci_access_msi(dev, PCIR_MSI_PENDING, &val, true); in pci_set_msi_pending()
1184 pci_emul_add_msicap(struct pci_vdev *dev, int msgnum) in pci_emul_add_msicap() argument
1189 pci_emul_add_capability(dev, (u_char *)&msicap, sizeof(msicap)); in pci_emul_add_msicap()
1217 pci_msix_table_init(struct pci_vdev *dev, int table_entries) in pci_msix_table_init() argument
1222 dev->msix.table = calloc(1, table_size); in pci_msix_table_init()
1223 if (!dev->msix.table) { in pci_msix_table_init()
1230 dev->msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; in pci_msix_table_init()
1236 pci_emul_add_msixcap(struct pci_vdev *dev, int msgnum, int barnum) in pci_emul_add_msixcap() argument
1251 dev->msix.table_bar = barnum; in pci_emul_add_msixcap()
1252 dev->msix.pba_bar = barnum; in pci_emul_add_msixcap()
1253 dev->msix.table_offset = 0; in pci_emul_add_msixcap()
1254 dev->msix.table_count = msgnum; in pci_emul_add_msixcap()
1255 dev->msix.pba_offset = tab_size; in pci_emul_add_msixcap()
1256 dev->msix.pba_size = PBA_SIZE(msgnum); in pci_emul_add_msixcap()
1258 if (pci_msix_table_init(dev, msgnum) != 0) in pci_emul_add_msixcap()
1264 pci_emul_alloc_bar(dev, barnum, PCIBAR_MEM32, in pci_emul_add_msixcap()
1265 tab_size + dev->msix.pba_size); in pci_emul_add_msixcap()
1267 return (pci_emul_add_capability(dev, (u_char *)&msixcap, in pci_emul_add_msixcap()
1282 msixcap_cfgwrite(struct pci_vdev *dev, int capoff, int offset, in msixcap_cfgwrite() argument
1293 msgctrl = pci_get_cfgdata16(dev, offset); in msixcap_cfgwrite()
1298 dev->msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; in msixcap_cfgwrite()
1299 dev->msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; in msixcap_cfgwrite()
1300 pci_lintr_update(dev); in msixcap_cfgwrite()
1303 CFGWRITE(dev, offset, val, bytes); in msixcap_cfgwrite()
1307 msicap_cfgwrite(struct pci_vdev *dev, int capoff, int offset, in msicap_cfgwrite() argument
1320 msgctrl = pci_get_cfgdata16(dev, offset); in msicap_cfgwrite()
1325 addrlo = pci_get_cfgdata32(dev, capoff + 4); in msicap_cfgwrite()
1327 msgdata = pci_get_cfgdata16(dev, capoff + 12); in msicap_cfgwrite()
1329 msgdata = pci_get_cfgdata16(dev, capoff + 8); in msicap_cfgwrite()
1332 dev->msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; in msicap_cfgwrite()
1333 if (dev->msi.enabled) { in msicap_cfgwrite()
1334 dev->msi.addr = addrlo; in msicap_cfgwrite()
1335 dev->msi.msg_data = msgdata; in msicap_cfgwrite()
1336 dev->msi.maxmsgnum = 1 << (mme >> 4); in msicap_cfgwrite()
1338 dev->msi.maxmsgnum = 0; in msicap_cfgwrite()
1340 pci_lintr_update(dev); in msicap_cfgwrite()
1343 CFGWRITE(dev, offset, val, bytes); in msicap_cfgwrite()
1344 if (dev->msi.enabled) { in msicap_cfgwrite()
1345 for (i = 0; i < dev->msi.maxmsgnum; i++) { in msicap_cfgwrite()
1346 if (!pci_is_msi_masked(dev, i) in msicap_cfgwrite()
1347 && pci_is_msi_pending(dev, i)) { in msicap_cfgwrite()
1348 pci_generate_msi(dev, i); in msicap_cfgwrite()
1355 pciecap_cfgwrite(struct pci_vdev *dev, int capoff, int offset, in pciecap_cfgwrite() argument
1359 CFGWRITE(dev, offset, val, bytes); in pciecap_cfgwrite()
1364 pci_emul_add_pciecap(struct pci_vdev *dev, int type) in pci_emul_add_pciecap() argument
1379 err = pci_emul_add_capability(dev, (u_char *)&pciecap, sizeof(pciecap)); in pci_emul_add_pciecap()
1388 pci_emul_capwrite(struct pci_vdev *dev, int offset, int bytes, uint32_t val) in pci_emul_capwrite() argument
1400 nextoff = pci_get_cfgdata8(dev, capoff + 1); in pci_emul_capwrite()
1424 capid = pci_get_cfgdata8(dev, capoff); in pci_emul_capwrite()
1427 msicap_cfgwrite(dev, capoff, offset, bytes, val); in pci_emul_capwrite()
1430 msixcap_cfgwrite(dev, capoff, offset, bytes, val); in pci_emul_capwrite()
1433 pciecap_cfgwrite(dev, capoff, offset, bytes, val); in pci_emul_capwrite()
1436 CFGWRITE(dev, offset, val, bytes); in pci_emul_capwrite()
1442 pci_emul_iscap(struct pci_vdev *dev, int offset) in pci_emul_iscap() argument
1446 sts = pci_get_cfgdata16(dev, PCIR_STATUS); in pci_emul_iscap()
1448 if (offset >= CAP_START_OFFSET && offset <= dev->capend) in pci_emul_iscap()
1817 struct pci_vdev *dev; in pci_bus_write_dsdt() local
1950 dev = si->si_funcs[func].fi_devi; in pci_bus_write_dsdt()
1951 if (dev != NULL && in pci_bus_write_dsdt()
1952 dev->dev_ops->vdev_write_dsdt != NULL) in pci_bus_write_dsdt()
1953 dev->dev_ops->vdev_write_dsdt(dev); in pci_bus_write_dsdt()
1988 pci_msi_enabled(struct pci_vdev *dev) in pci_msi_enabled() argument
1990 return dev->msi.enabled; in pci_msi_enabled()
1994 pci_msi_maxmsgnum(struct pci_vdev *dev) in pci_msi_maxmsgnum() argument
1996 if (dev->msi.enabled) in pci_msi_maxmsgnum()
1997 return dev->msi.maxmsgnum; in pci_msi_maxmsgnum()
2003 pci_msix_enabled(struct pci_vdev *dev) in pci_msix_enabled() argument
2005 return (dev->msix.enabled && !dev->msi.enabled); in pci_msix_enabled()
2015 pci_generate_msix(struct pci_vdev *dev, int index) in pci_generate_msix() argument
2019 if (!pci_msix_enabled(dev)) in pci_generate_msix()
2022 if (dev->msix.function_mask) in pci_generate_msix()
2025 if (index >= dev->msix.table_count) in pci_generate_msix()
2028 mte = &dev->msix.table[index]; in pci_generate_msix()
2031 vm_lapic_msi(dev->vmctx, mte->addr, mte->msg_data); in pci_generate_msix()
2042 pci_generate_msi(struct pci_vdev *dev, int index) in pci_generate_msi() argument
2044 if (pci_msi_enabled(dev) && index < pci_msi_maxmsgnum(dev)) { in pci_generate_msi()
2045 if (pci_is_msi_masked(dev, index)) { in pci_generate_msi()
2046 pci_set_msi_pending(dev, index, true); in pci_generate_msi()
2049 vm_lapic_msi(dev->vmctx, dev->msi.addr, in pci_generate_msi()
2050 dev->msi.msg_data + index); in pci_generate_msi()
2051 pci_set_msi_pending(dev, index, false); in pci_generate_msi()
2056 pci_lintr_permitted(struct pci_vdev *dev) in pci_lintr_permitted() argument
2060 cmd = pci_get_cfgdata16(dev, PCIR_COMMAND); in pci_lintr_permitted()
2061 return (!(dev->msi.enabled || dev->msix.enabled || in pci_lintr_permitted()
2066 pci_lintr_request(struct pci_vdev *dev) in pci_lintr_request() argument
2072 bi = pci_businfo[dev->bus]; in pci_lintr_request()
2074 pr_err("%s: pci [%s] has wrong bus %d info!\n", __func__, dev->name, dev->bus); in pci_lintr_request()
2082 si = &bi->slotinfo[dev->slot]; in pci_lintr_request()
2093 dev->lintr.pin = bestpin + 1; in pci_lintr_request()
2094 pci_set_cfgdata8(dev, PCIR_INTPIN, bestpin + 1); in pci_lintr_request()
2098 pci_lintr_release(struct pci_vdev *dev) in pci_lintr_release() argument
2104 bi = pci_businfo[dev->bus]; in pci_lintr_release()
2106 pr_err("%s: pci [%s] has wrong bus %d info!\n", __func__, dev->name, dev->bus); in pci_lintr_release()
2110 si = &bi->slotinfo[dev->slot]; in pci_lintr_release()
2120 pci_lintr_route(struct pci_vdev *dev) in pci_lintr_route() argument
2125 if (dev->lintr.pin == 0) in pci_lintr_route()
2128 bi = pci_businfo[dev->bus]; in pci_lintr_route()
2130 pr_err("%s: pci [%s] has wrong bus %d info!\n", __func__, dev->name, dev->bus); in pci_lintr_route()
2133 ii = &bi->slotinfo[dev->slot].si_intpins[dev->lintr.pin - 1]; in pci_lintr_route()
2140 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(dev); in pci_lintr_route()
2147 ii->ii_pirq_pin = pirq_alloc_pin(dev); in pci_lintr_route()
2149 dev->lintr.ioapic_irq = ii->ii_ioapic_irq; in pci_lintr_route()
2150 dev->lintr.pirq_pin = ii->ii_pirq_pin; in pci_lintr_route()
2151 pci_set_cfgdata8(dev, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); in pci_lintr_route()
2153 vm_set_gsi_irq(dev->vmctx, ii->ii_ioapic_irq, GSI_SET_HIGH); in pci_lintr_route()
2162 pci_lintr_assert(struct pci_vdev *dev) in pci_lintr_assert() argument
2164 if (dev->lintr.pin <= 0) { in pci_lintr_assert()
2165 pr_warn("%s: Invalid intr pin on dev [%s]\n", __func__, dev->name); in pci_lintr_assert()
2169 pthread_mutex_lock(&dev->lintr.lock); in pci_lintr_assert()
2170 if (dev->lintr.state == IDLE) { in pci_lintr_assert()
2171 if (pci_lintr_permitted(dev)) { in pci_lintr_assert()
2172 dev->lintr.state = ASSERTED; in pci_lintr_assert()
2173 pci_irq_assert(dev); in pci_lintr_assert()
2175 dev->lintr.state = PENDING; in pci_lintr_assert()
2177 pthread_mutex_unlock(&dev->lintr.lock); in pci_lintr_assert()
2186 pci_lintr_deassert(struct pci_vdev *dev) in pci_lintr_deassert() argument
2188 if (dev->lintr.pin <= 0) { in pci_lintr_deassert()
2189 pr_warn("%s: Invalid intr pin on dev [%s]\n", __func__, dev->name); in pci_lintr_deassert()
2193 pthread_mutex_lock(&dev->lintr.lock); in pci_lintr_deassert()
2194 if (dev->lintr.state == ASSERTED) { in pci_lintr_deassert()
2195 dev->lintr.state = IDLE; in pci_lintr_deassert()
2196 pci_irq_deassert(dev); in pci_lintr_deassert()
2197 } else if (dev->lintr.state == PENDING) in pci_lintr_deassert()
2198 dev->lintr.state = IDLE; in pci_lintr_deassert()
2199 pthread_mutex_unlock(&dev->lintr.lock); in pci_lintr_deassert()
2203 pci_lintr_update(struct pci_vdev *dev) in pci_lintr_update() argument
2205 pthread_mutex_lock(&dev->lintr.lock); in pci_lintr_update()
2206 if (dev->lintr.state == ASSERTED && !pci_lintr_permitted(dev)) { in pci_lintr_update()
2207 pci_irq_deassert(dev); in pci_lintr_update()
2208 dev->lintr.state = PENDING; in pci_lintr_update()
2209 } else if (dev->lintr.state == PENDING && pci_lintr_permitted(dev)) { in pci_lintr_update()
2210 dev->lintr.state = ASSERTED; in pci_lintr_update()
2211 pci_irq_assert(dev); in pci_lintr_update()
2213 pthread_mutex_unlock(&dev->lintr.lock); in pci_lintr_update()
2309 pci_emul_cmdsts_write(struct pci_vdev *dev, int coff, uint32_t new, int bytes) in pci_emul_cmdsts_write() argument
2314 cmd = pci_get_cfgdata16(dev, PCIR_COMMAND); /* stash old value */ in pci_emul_cmdsts_write()
2326 old = CFGREAD(dev, coff, bytes); in pci_emul_cmdsts_write()
2329 CFGWRITE(dev, coff, new, bytes); /* update config */ in pci_emul_cmdsts_write()
2331 cmd2 = pci_get_cfgdata16(dev, PCIR_COMMAND); /* get updated value */ in pci_emul_cmdsts_write()
2339 switch (dev->bar[i].type) { in pci_emul_cmdsts_write()
2346 if (porten(dev)) in pci_emul_cmdsts_write()
2347 register_bar(dev, i); in pci_emul_cmdsts_write()
2349 unregister_bar(dev, i); in pci_emul_cmdsts_write()
2356 if (memen(dev)) in pci_emul_cmdsts_write()
2357 register_bar(dev, i); in pci_emul_cmdsts_write()
2359 unregister_bar(dev, i); in pci_emul_cmdsts_write()
2363 pr_err("%s: invalid bar type %d\n", __func__, dev->bar[i].type); in pci_emul_cmdsts_write()
2372 pci_lintr_update(dev); in pci_emul_cmdsts_write()
2381 struct pci_vdev *dev; in pci_cfgrw() local
2391 dev = si->si_funcs[func].fi_devi; in pci_cfgrw()
2393 dev = NULL; in pci_cfgrw()
2399 if (dev == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || in pci_cfgrw()
2406 ops = dev->dev_ops; in pci_cfgrw()
2440 needcfg = ops->vdev_cfgread(ctx, vcpu, dev, coff, bytes, in pci_cfgrw()
2447 *eax = CFGREAD(dev, coff, bytes); in pci_cfgrw()
2453 (*ops->vdev_cfgwrite)(ctx, vcpu, dev, in pci_cfgrw()
2468 mask = ~(dev->bar[idx].size - 1); in pci_cfgrw()
2470 if (dev->bar[idx].type == PCIBAR_IO) in pci_cfgrw()
2471 decode = porten(dev); in pci_cfgrw()
2473 decode = memen(dev); in pci_cfgrw()
2484 if (!dev->bar[idx].sizing && (*eax == ~0U)) { in pci_cfgrw()
2485 dev->bar[idx].sizing = true; in pci_cfgrw()
2487 } else if (dev->bar[idx].sizing && (*eax != ~0U)) { in pci_cfgrw()
2488 dev->bar[idx].sizing = false; in pci_cfgrw()
2494 mmio_bar_prop = pci_get_cfgdata32(dev, PCIR_BAR(idx)) & in pci_cfgrw()
2498 switch (dev->bar[idx].type) { in pci_cfgrw()
2500 dev->bar[idx].addr = bar = 0; in pci_cfgrw()
2509 if (addr != dev->bar[idx].addr) { in pci_cfgrw()
2510 update_bar_address(ctx, dev, addr, idx, in pci_cfgrw()
2519 if (addr != dev->bar[idx].addr) { in pci_cfgrw()
2520 update_bar_address(ctx, dev, addr, idx, in pci_cfgrw()
2529 if (addr != (uint32_t)dev->bar[idx].addr) { in pci_cfgrw()
2530 update_bar_address(ctx, dev, addr, idx, in pci_cfgrw()
2536 mask = ~(dev->bar[idx - 1].size - 1); in pci_cfgrw()
2539 if (bar != dev->bar[idx - 1].addr >> 32) { in pci_cfgrw()
2540 update_bar_address(ctx, dev, addr, idx - 1, in pci_cfgrw()
2546 pr_err("%s: invalid bar type %d\n", __func__, dev->bar[idx].type); in pci_cfgrw()
2549 pci_set_cfgdata32(dev, coff, bar); in pci_cfgrw()
2553 } else if (pci_emul_iscap(dev, coff)) { in pci_cfgrw()
2554 pci_emul_capwrite(dev, coff, bytes, *eax); in pci_cfgrw()
2556 pci_emul_cmdsts_write(dev, coff, *eax, bytes); in pci_cfgrw()
2558 CFGWRITE(dev, coff, *eax, bytes); in pci_cfgrw()
2588 pci_emul_dinit(struct vmctx *ctx, struct pci_vdev *dev, char *opts) in pci_emul_dinit() argument
2594 dev->arg = dummy; in pci_emul_dinit()
2596 pci_set_cfgdata16(dev, PCIR_DEVICE, 0x0001); in pci_emul_dinit()
2597 pci_set_cfgdata16(dev, PCIR_VENDOR, 0x10DD); in pci_emul_dinit()
2598 pci_set_cfgdata8(dev, PCIR_CLASS, 0x02); in pci_emul_dinit()
2600 return pci_emul_add_msicap(dev, PCI_EMUL_MSI_MSGS) || in pci_emul_dinit()
2601 pci_emul_alloc_bar(dev, 0, PCIBAR_IO, DIOSZ) || in pci_emul_dinit()
2602 pci_emul_alloc_bar(dev, 1, PCIBAR_MEM32, DMEMSZ) || in pci_emul_dinit()
2603 pci_emul_alloc_bar(dev, 2, PCIBAR_MEM32, DMEMSZ); in pci_emul_dinit()
2607 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_vdev *dev, int baridx, in pci_emul_diow() argument
2612 struct pci_emul_dummy *dummy = dev->arg; in pci_emul_diow()
2634 if (offset == 4 && size == 4 && pci_msi_enabled(dev)) in pci_emul_diow()
2635 pci_generate_msi(dev, value % pci_msi_maxmsgnum(dev)); in pci_emul_diow()
2638 for (i = 0; i < pci_msi_maxmsgnum(dev); i++) in pci_emul_diow()
2639 pci_generate_msi(dev, i); in pci_emul_diow()
2674 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_vdev *dev, int baridx, in pci_emul_dior() argument
2677 struct pci_emul_dummy *dummy = dev->arg; in pci_emul_dior()
2737 struct pci_vdev *dev = NULL; in pci_get_vdev_info() local
2747 dev = si->si_funcs[0].fi_devi; in pci_get_vdev_info()
2751 return dev; in pci_get_vdev_info()