Lines Matching refs:reg_width
28 uint32_t reg_width; member
36 .reg_width = 1,
43 .reg_width = 4,
50 .reg_width = 1,
62 return pio_read8(uart.port_address + (reg_idx * uart.reg_width)); in uart16550_read_reg()
64 if (uart.reg_width == 4U) { in uart16550_read_reg()
65 return mmio_read32(uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_read_reg()
67 return mmio_read8(uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_read_reg()
78 pio_write8(val, uart.port_address + (reg_idx * uart.reg_width)); in uart16550_write_reg()
80 if (uart.reg_width == 4U) { in uart16550_write_reg()
81 mmio_write32(val, uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_write_reg()
83 mmio_write8(val, uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_write_reg()
184 uart.reg_width = 1; in uart16550_init()
292 uart.reg_width = 4; in uart16550_set_property()
295 uart.reg_width = 1; in uart16550_set_property()