Lines Matching refs:uart
32 static struct console_uart uart = { variable
39 static struct console_uart uart = { variable
46 static struct console_uart uart = { variable
59 static inline uint32_t uart16550_read_reg(struct console_uart uart, uint16_t reg_idx) in uart16550_read_reg() argument
61 if (uart.type == PIO) { in uart16550_read_reg()
62 return pio_read8(uart.port_address + (reg_idx * uart.reg_width)); in uart16550_read_reg()
64 if (uart.reg_width == 4U) { in uart16550_read_reg()
65 return mmio_read32(uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_read_reg()
67 return mmio_read8(uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_read_reg()
75 static inline void uart16550_write_reg(struct console_uart uart, uint32_t val, uint16_t reg_idx) in uart16550_write_reg() argument
77 if (uart.type == PIO) { in uart16550_write_reg()
78 pio_write8(val, uart.port_address + (reg_idx * uart.reg_width)); in uart16550_write_reg()
80 if (uart.reg_width == 4U) { in uart16550_write_reg()
81 mmio_write32(val, uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_write_reg()
83 mmio_write8(val, uart.mmio_base_vaddr + (reg_idx * uart.reg_width)); in uart16550_write_reg()
111 temp_reg = uart16550_read_reg(uart, UART16550_LCR); in uart16550_set_baud_rate()
113 uart16550_write_reg(uart, temp_reg, UART16550_LCR); in uart16550_set_baud_rate()
116 uart16550_write_reg(uart, ((baud_div >> 8U) & 0xFFU), UART16550_DLM); in uart16550_set_baud_rate()
117 uart16550_write_reg(uart, (baud_div & 0xFFU), UART16550_DLL); in uart16550_set_baud_rate()
121 uart16550_write_reg(uart, temp_reg, UART16550_LCR); in uart16550_set_baud_rate()
157 if (!uart.enabled) { in uart16550_init()
162 if (uart.type == MMIO) { in uart16550_init()
163 mmio_base_va = hpa2hva(hva2hpa_early(uart.mmio_base_vaddr)); in uart16550_init()
172 if (uart.type == PCI) { in uart16550_init()
173 uint32_t bar0 = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(0), 4U); in uart16550_init()
177 uart.enabled = false; in uart16550_init()
180 uint16_t cmd = (uint16_t)pci_pdev_read_cfg(uart.bdf, PCIR_COMMAND, 2U); in uart16550_init()
182 uart.type = PIO; in uart16550_init()
183 uart.port_address = (uint16_t)(bar0 & PCI_BASE_ADDRESS_IO_MASK); in uart16550_init()
184 uart.reg_width = 1; in uart16550_init()
185 pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN); in uart16550_init()
187 uart.type = MMIO; in uart16550_init()
188 uint32_t bar_hi = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U); in uart16550_init()
193 uart.mmio_base_vaddr = hpa2hva_early(addr); in uart16550_init()
194 pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN); in uart16550_init()
196 uart.enabled = false; in uart16550_init()
202 spinlock_init(&uart.rx_lock); in uart16550_init()
203 spinlock_init(&uart.tx_lock); in uart16550_init()
206 uart16550_write_reg(uart, FCR_FIFOE | FCR_RFR | FCR_TFR, UART16550_FCR); in uart16550_init()
209 uart16550_write_reg(uart, (LCR_WL8 | LCR_NB_STOP_BITS_1 | LCR_PARITY_NONE), UART16550_LCR); in uart16550_init()
212 uart16550_write_reg(uart, UART_IER_DISABLE_ALL, UART16550_IER); in uart16550_init()
218 uart16550_write_reg(uart, MCR_RTS | MCR_DTR, UART16550_MCR); in uart16550_init()
226 if (!uart.enabled) { in uart16550_getc()
230 spinlock_irqsave_obtain(&uart.rx_lock, &rflags); in uart16550_getc()
232 if ((uart16550_read_reg(uart, UART16550_LSR) & LSR_DR) == LSR_DR) { in uart16550_getc()
234 ret = uart16550_read_reg(uart, UART16550_RBR); in uart16550_getc()
237 spinlock_irqrestore_release(&uart.rx_lock, rflags); in uart16550_getc()
251 reg = uart16550_read_reg(uart, UART16550_LSR); in uart16550_putc()
256 uart16550_write_reg(uart, (uint32_t)temp, UART16550_THR); in uart16550_putc()
264 if (!uart.enabled) { in uart16550_puts()
268 spinlock_irqsave_obtain(&uart.tx_lock, &rflags); in uart16550_puts()
278 spinlock_irqrestore_release(&uart.tx_lock, rflags); in uart16550_puts()
284 uart.enabled = enabled; in uart16550_set_property()
285 uart.type = uart_type; in uart16550_set_property()
286 uart.bdf.value = 0U; in uart16550_set_property()
289 uart.port_address = data; in uart16550_set_property()
291 uart.bdf.value = data; in uart16550_set_property()
292 uart.reg_width = 4; in uart16550_set_property()
294 uart.mmio_base_vaddr = (void *)data; in uart16550_set_property()
295 uart.reg_width = 1; in uart16550_set_property()
303 if (uart.enabled && (uart.bdf.value != 0)) { in is_pci_dbg_uart()
304 if (bdf_value.value == uart.bdf.value) { in is_pci_dbg_uart()
316 if (uart.enabled && (uart.type == PIO)) { in get_pio_dbg_uart_cfg()
317 *pio_address = uart.port_address; in get_pio_dbg_uart_cfg()