Lines Matching refs:pdev
238 bool pdev_need_bar_restore(const struct pci_pdev *pdev) in pdev_need_bar_restore() argument
243 for (idx = 0U; idx < pdev->nr_bars; idx++) { in pdev_need_bar_restore()
244 bar = pci_pdev_read_cfg(pdev->bdf, pci_bar_offset(idx), 4U); in pdev_need_bar_restore()
245 if (bar != pdev->bars[idx].phy_bar) { in pdev_need_bar_restore()
263 static inline void pdev_save_bar(struct pci_pdev *pdev) in pdev_save_bar() argument
267 for (idx = 0U; idx < pdev->nr_bars; idx++) { in pdev_save_bar()
268 get_pci_bar_resource(pdev->bdf, pci_bar_offset(idx), &pdev->bars[idx]); in pdev_save_bar()
272 void pdev_restore_bar(const struct pci_pdev *pdev) in pdev_restore_bar() argument
276 for (idx = 0U; idx < pdev->nr_bars; idx++) { in pdev_restore_bar()
277 pci_pdev_write_cfg(pdev->bdf, pci_bar_offset(idx), 4U, pdev->bars[idx].phy_bar); in pdev_restore_bar()
307 const struct pci_pdev *pdev = pci_find_pdev(pbdf); in pci_lookup_drhd_for_pbdf() local
308 return (pdev != NULL) ? pdev->drhd_index : INVALID_DRHD_INDEX; in pci_lookup_drhd_for_pbdf()
423 struct pci_pdev *pdev; in scan_pci_hierarchy() local
465 pdev = pci_init_pdev(pbdf, bdf_drhd_index); in scan_pci_hierarchy()
467 if ((pdev != NULL) && is_bridge(pdev)) { in scan_pci_hierarchy()
544 static void config_pci_bridge(const struct pci_pdev *pdev) in config_pci_bridge() argument
549 val = pci_pdev_read_cfg(pdev->bdf, PCIR_COMMAND, 2U); in config_pci_bridge()
550 pci_pdev_write_cfg(pdev->bdf, PCIR_COMMAND, 2U, (uint16_t)val | PCIM_CMD_INTxDIS); in config_pci_bridge()
553 if (pdev->msi_capoff != 0x00UL) { in config_pci_bridge()
554 offset = pdev->msi_capoff + PCIR_MSI_CTRL; in config_pci_bridge()
556 msgctrl = pci_pdev_read_cfg(pdev->bdf, offset, 2U); in config_pci_bridge()
558 pci_pdev_write_cfg(pdev->bdf, offset, 2U, msgctrl); in config_pci_bridge()
562 if (pdev->pcie_capoff != 0x00UL) { in config_pci_bridge()
563 offset = pdev->pcie_capoff + PCIR_PCIE_DEVCAP2; in config_pci_bridge()
564 val = pci_pdev_read_cfg(pdev->bdf, offset, 2U); in config_pci_bridge()
567 offset = pdev->pcie_capoff + PCIR_PCIE_DEVCTL2; in config_pci_bridge()
569 val = pci_pdev_read_cfg(pdev->bdf, offset, 2U); in config_pci_bridge()
571 pci_pdev_write_cfg(pdev->bdf, offset, 2U, val); in config_pci_bridge()
585 struct pci_pdev *pdev = NULL; in init_all_dev_config() local
588 pdev = &pci_pdevs[idx]; in init_all_dev_config()
590 if (is_bridge(pdev)) { in init_all_dev_config()
591 config_pci_bridge(pdev); in init_all_dev_config()
598 if (pdev->sriov.capoff != 0U) { in init_all_dev_config()
599 cnt = pci_pdev_read_cfg(pdev->bdf, in init_all_dev_config()
600 pdev->sriov.capoff + PCIR_SRIOV_TOTAL_VFS, 2U); in init_all_dev_config()
607 __func__, pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f, cnt); in init_all_dev_config()
613 (void)init_one_dev_config(pdev); in init_all_dev_config()
669 static void pci_enable_ptm_root(struct pci_pdev *pdev, uint32_t pos) in pci_enable_ptm_root() argument
673 cap = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PTM_CAP, PCI_PTM_CAP_LEN); in pci_enable_ptm_root()
678 pci_pdev_write_cfg(pdev->bdf, pos + PCIR_PTM_CTRL, 4, ctrl); in pci_enable_ptm_root()
680 ctrl = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PTM_CTRL, 4); in pci_enable_ptm_root()
683 pdev->bdf.bits.b, pdev->bdf.bits.d, in pci_enable_ptm_root()
684 pdev->bdf.bits.f, pos, (ctrl & PCIM_PTM_CTRL_ENABLED) != 0, in pci_enable_ptm_root()
690 pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enable_ptm_root()
700 static void pci_enumerate_ext_cap(struct pci_pdev *pdev) in pci_enumerate_ext_cap() argument
714 hdr = pci_pdev_read_cfg(pdev->bdf, pos, 4U); in pci_enumerate_ext_cap()
717 pdev->sriov.capoff = pos; in pci_enumerate_ext_cap()
718 pdev->sriov.caplen = PCI_SRIOV_CAP_LEN; in pci_enumerate_ext_cap()
719 pdev->sriov.pre_pos = pre_pos; in pci_enumerate_ext_cap()
721 pcie_dev_type = (((uint8_t)pci_pdev_read_cfg(pdev->bdf, in pci_enumerate_ext_cap()
722 pdev->pcie_capoff + PCIER_FLAGS, 1)) & PCIEM_FLAGS_TYPE) >> 4; in pci_enumerate_ext_cap()
730 pdev->bdf.bits.b, in pci_enumerate_ext_cap()
731 pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enumerate_ext_cap()
736 pci_enable_ptm_root(pdev, pos); in pci_enumerate_ext_cap()
743 pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enumerate_ext_cap()
756 pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f, pos); in pci_enumerate_ext_cap()
759 hdr = pci_pdev_read_cfg(pdev->bdf, pos, 4U); in pci_enumerate_ext_cap()
765 capability region detected\n", __func__, pdev->bdf.bits.b, in pci_enumerate_ext_cap()
766 pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enumerate_ext_cap()
773 static void pci_enumerate_cap(struct pci_pdev *pdev) in pci_enumerate_cap() argument
782 pos = (uint8_t)pci_pdev_read_cfg(pdev->bdf, PCIR_CAP_PTR, 1U); in pci_enumerate_cap()
785 cap = (uint8_t)pci_pdev_read_cfg(pdev->bdf, pos + PCICAP_ID, 1U); in pci_enumerate_cap()
788 pdev->msi_capoff = pos; in pci_enumerate_cap()
790 pdev->msix.capoff = pos; in pci_enumerate_cap()
791 pdev->msix.caplen = MSIX_CAPLEN; in pci_enumerate_cap()
792 len = pdev->msix.caplen; in pci_enumerate_cap()
794 msgctrl = pci_pdev_read_cfg(pdev->bdf, pdev->msix.capoff + PCIR_MSIX_CTRL, 2U); in pci_enumerate_cap()
797 table_info = pci_pdev_read_cfg(pdev->bdf, pdev->msix.capoff + PCIR_MSIX_TABLE, 4U); in pci_enumerate_cap()
799 pdev->msix.table_bar = (uint8_t)(table_info & PCIM_MSIX_BIR_MASK); in pci_enumerate_cap()
801 pdev->msix.table_offset = table_info & ~PCIM_MSIX_BIR_MASK; in pci_enumerate_cap()
802 pdev->msix.table_count = (msgctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U; in pci_enumerate_cap()
804 ASSERT(pdev->msix.table_count <= CONFIG_MAX_MSIX_TABLE_NUM); in pci_enumerate_cap()
808 pdev->msix.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, (uint32_t)pos + idx, 1U); in pci_enumerate_cap()
811 val = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PMCSR, 4U); in pci_enumerate_cap()
812 pdev->has_pm_reset = ((val & PCIM_PMCSR_NO_SOFT_RST) == 0U); in pci_enumerate_cap()
815 pcie_devcap = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PCIE_DEVCAP, 4U); in pci_enumerate_cap()
816 pdev->pcie_capoff = pos; in pci_enumerate_cap()
817 pdev->has_flr = ((pcie_devcap & PCIM_PCIE_FLRCAP) != 0U); in pci_enumerate_cap()
819 val = pci_pdev_read_cfg(pdev->bdf, pos, 4U); in pci_enumerate_cap()
820 pdev->has_af_flr = ((val & PCIM_AF_FLR_CAP) != 0U); in pci_enumerate_cap()
825 pos = (uint8_t)pci_pdev_read_cfg(pdev->bdf, pos + PCICAP_NEXTPTR, 1U); in pci_enumerate_cap()
829 pci_enumerate_ext_cap(pdev); in pci_enumerate_cap()
847 struct pci_pdev *pdev = NULL; in pci_init_pdev() local
855 pdev = &pci_pdevs[num_pci_pdev]; in pci_init_pdev()
856 pdev->bdf = bdf; in pci_init_pdev()
857 pdev->hdr_type = hdr_type; in pci_init_pdev()
858 pdev->base_class = (uint8_t)pci_pdev_read_cfg(bdf, PCIR_CLASS, 1U); in pci_init_pdev()
859 pdev->sub_class = (uint8_t)pci_pdev_read_cfg(bdf, PCIR_SUBCLASS, 1U); in pci_init_pdev()
860 pdev->nr_bars = pci_pdev_get_nr_bars(hdr_type); in pci_init_pdev()
861 pdev_save_bar(pdev); in pci_init_pdev()
864 pci_enumerate_cap(pdev); in pci_init_pdev()
875 hv_owned_pci_pdevs[num_hv_owned_pci_pdev] = pdev; in pci_init_pdev()
878 hlist_add_head(&pdev->link, &pdevs_hlist_heads[hash64(bdf.value, PDEV_HLIST_HASHBITS)]); in pci_init_pdev()
879 pdev->drhd_index = drhd_index; in pci_init_pdev()
881 reserve_vmsix_on_msi_irtes(pdev); in pci_init_pdev()
890 return pdev; in pci_init_pdev()