1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright (c) 2017-2022 Intel Corporation. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * BSD LICENSE 19 * 20 * Copyright (C) 2017-2022 Intel Corporation. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * $FreeBSD$ 44 */ 45 46 /** 47 * @file hsm_ioctl_defs.h 48 * 49 * @brief Hypervisor Module definition for ioctl to user space 50 */ 51 52 #ifndef _VHM_IOCTL_DEFS_H_ 53 #define _VHM_IOCTL_DEFS_H_ 54 55 #include <linux/types.h> 56 57 /* Commmon structures for ACRN/HSM/DM */ 58 #include "acrn_common.h" 59 60 /* The ioctl type, documented in ioctl-number.rst */ 61 #define ACRN_IOCTL_TYPE 0xA2 62 63 /* 64 * Commmon IOCTL ID defination for HSM/DM 65 */ 66 #define _IC_ID(x, y) (((x)<<24)|(y)) 67 #define IC_ID 0x43UL 68 69 /* 70 * Common IOCTL IDs definition for ACRN userspace 71 */ 72 #define ACRN_IOCTL_CREATE_VM \ 73 _IOWR(ACRN_IOCTL_TYPE, 0x10, struct acrn_vm_creation) 74 #define ACRN_IOCTL_DESTROY_VM \ 75 _IO(ACRN_IOCTL_TYPE, 0x11) 76 #define ACRN_IOCTL_START_VM \ 77 _IO(ACRN_IOCTL_TYPE, 0x12) 78 #define ACRN_IOCTL_PAUSE_VM \ 79 _IO(ACRN_IOCTL_TYPE, 0x13) 80 #define ACRN_IOCTL_RESET_VM \ 81 _IO(ACRN_IOCTL_TYPE, 0x15) 82 #define ACRN_IOCTL_SET_VCPU_REGS \ 83 _IOW(ACRN_IOCTL_TYPE, 0x16, struct acrn_vcpu_regs) 84 85 /* IRQ and Interrupts */ 86 #define ACRN_IOCTL_INJECT_MSI \ 87 _IOW(ACRN_IOCTL_TYPE, 0x23, struct acrn_msi_entry) 88 #define ACRN_IOCTL_VM_INTR_MONITOR \ 89 _IOW(ACRN_IOCTL_TYPE, 0x24, unsigned long) 90 #define ACRN_IOCTL_SET_IRQLINE \ 91 _IOW(ACRN_IOCTL_TYPE, 0x25, __u64) 92 93 /* DM ioreq management */ 94 #define ACRN_IOCTL_NOTIFY_REQUEST_FINISH \ 95 _IOW(ACRN_IOCTL_TYPE, 0x31, struct acrn_ioreq_notify) 96 #define ACRN_IOCTL_CREATE_IOREQ_CLIENT \ 97 _IO(ACRN_IOCTL_TYPE, 0x32) 98 #define ACRN_IOCTL_ATTACH_IOREQ_CLIENT \ 99 _IO(ACRN_IOCTL_TYPE, 0x33) 100 #define ACRN_IOCTL_DESTROY_IOREQ_CLIENT \ 101 _IO(ACRN_IOCTL_TYPE, 0x34) 102 #define ACRN_IOCTL_CLEAR_VM_IOREQ \ 103 _IO(ACRN_IOCTL_TYPE, 0x35) 104 105 /* Guest memory management */ 106 #define ACRN_IOCTL_SET_MEMSEG \ 107 _IOW(ACRN_IOCTL_TYPE, 0x41, struct acrn_vm_memmap) 108 #define ACRN_IOCTL_UNSET_MEMSEG \ 109 _IOW(ACRN_IOCTL_TYPE, 0x42, struct acrn_vm_memmap) 110 111 /* PCI assignment*/ 112 #define ACRN_IOCTL_SET_PTDEV_INTR \ 113 _IOW(ACRN_IOCTL_TYPE, 0x53, struct acrn_ptdev_irq) 114 #define ACRN_IOCTL_RESET_PTDEV_INTR \ 115 _IOW(ACRN_IOCTL_TYPE, 0x54, struct acrn_ptdev_irq) 116 #define ACRN_IOCTL_ASSIGN_PCIDEV \ 117 _IOW(ACRN_IOCTL_TYPE, 0x55, struct acrn_pcidev) 118 #define ACRN_IOCTL_DEASSIGN_PCIDEV \ 119 _IOW(ACRN_IOCTL_TYPE, 0x56, struct acrn_pcidev) 120 #define ACRN_IOCTL_ASSIGN_MMIODEV \ 121 _IOW(ACRN_IOCTL_TYPE, 0x57, struct acrn_mmiodev) 122 #define ACRN_IOCTL_DEASSIGN_MMIODEV \ 123 _IOW(ACRN_IOCTL_TYPE, 0x58, struct acrn_mmiodev) 124 #define ACRN_IOCTL_CREATE_VDEV \ 125 _IOW(ACRN_IOCTL_TYPE, 0x59, struct acrn_vdev) 126 #define ACRN_IOCTL_DESTROY_VDEV \ 127 _IOW(ACRN_IOCTL_TYPE, 0x5A, struct acrn_vdev) 128 129 /* Power management */ 130 #define ACRN_IOCTL_PM_GET_CPU_STATE \ 131 _IOWR(ACRN_IOCTL_TYPE, 0x60, __u64) 132 133 /* HSM eventfd */ 134 #define ACRN_IOCTL_IOEVENTFD \ 135 _IOW(ACRN_IOCTL_TYPE, 0x70, struct acrn_ioeventfd) 136 #define ACRN_IOCTL_IRQFD \ 137 _IOW(ACRN_IOCTL_TYPE, 0x71, struct acrn_irqfd) 138 139 /* Asynchronous IO */ 140 #define ACRN_IOCTL_SETUP_ASYNCIO \ 141 _IOW(ACRN_IOCTL_TYPE, 0x90, __u64) 142 143 /* VM EVENT */ 144 #define ACRN_IOCTL_SETUP_VM_EVENT_RING \ 145 _IOW(ACRN_IOCTL_TYPE, 0xa0, __u64) 146 #define ACRN_IOCTL_SETUP_VM_EVENT_FD \ 147 _IOW(ACRN_IOCTL_TYPE, 0xa1, int) 148 149 #define ACRN_MEM_ACCESS_RIGHT_MASK 0x00000007U 150 #define ACRN_MEM_ACCESS_READ 0x00000001U 151 #define ACRN_MEM_ACCESS_WRITE 0x00000002U 152 #define ACRN_MEM_ACCESS_EXEC 0x00000004U 153 #define ACRN_MEM_ACCESS_RWX (ACRN_MEM_ACCESS_READ | \ 154 ACRN_MEM_ACCESS_WRITE | \ 155 ACRN_MEM_ACCESS_EXEC) 156 157 #define ACRN_MEM_TYPE_MASK 0x000007C0U 158 #define ACRN_MEM_TYPE_WB 0x00000040U 159 #define ACRN_MEM_TYPE_WT 0x00000080U 160 #define ACRN_MEM_TYPE_UC 0x00000100U 161 #define ACRN_MEM_TYPE_WC 0x00000200U 162 #define ACRN_MEM_TYPE_WP 0x00000400U 163 164 /* Memory mapping types */ 165 #define ACRN_MEMMAP_RAM 0 166 #define ACRN_MEMMAP_MMIO 1 167 168 /** 169 * @brief EPT memory mapping info for guest 170 */ 171 struct acrn_vm_memmap { 172 /** memory mapping type */ 173 __u32 type; 174 /** memory mapping attribute */ 175 __u32 attr; 176 /** user OS guest physical start address of memory mapping */ 177 __u64 user_vm_pa; 178 union { 179 /** host physical start address of memory, 180 * only for type == VM_MMIO 181 */ 182 __u64 service_vm_pa; 183 /** service OS user virtual start address of 184 * memory, only for type == VM_MEMMAP_SYSMEM && 185 * using_vma == true 186 */ 187 __u64 vma_base; 188 }; 189 /** the length of memory range mapped */ 190 __u64 len; 191 }; 192 193 /* Type of interrupt of a passthrough device */ 194 #define ACRN_PTDEV_IRQ_INTX 0 195 #define ACRN_PTDEV_IRQ_MSI 1 196 #define ACRN_PTDEV_IRQ_MSIX 2 197 198 /** 199 * @brief pass thru device irq data structure 200 */ 201 struct acrn_ptdev_irq { 202 /** irq type */ 203 uint32_t type; 204 /** virtual bdf description of pass thru device */ 205 uint16_t virt_bdf; /* IN: Device virtual BDF# */ 206 /** physical bdf description of pass thru device */ 207 uint16_t phys_bdf; /* IN: Device physical BDF# */ 208 209 /** info of IOAPIC/PIC interrupt */ 210 struct { 211 /** virtual IOAPIC pin */ 212 uint32_t virt_pin; 213 /** physical IOAPIC pin */ 214 uint32_t phys_pin; 215 /** PIC pin */ 216 uint32_t is_pic_pin; 217 } intx; 218 }; 219 220 /** 221 * @brief data strcture to notify hypervisor ioreq is handled 222 */ 223 struct acrn_ioreq_notify { 224 /** VM id to identify ioreq client */ 225 __u16 vmid; 226 __u16 reserved; 227 /** identify the ioreq submitter */ 228 __u32 vcpu; 229 }; 230 231 #define ACRN_PLATFORM_LAPIC_IDS_MAX 64 232 struct acrn_ioeventfd { 233 #define ACRN_IOEVENTFD_FLAG_PIO 0x01 234 #define ACRN_IOEVENTFD_FLAG_DATAMATCH 0x02 235 #define ACRN_IOEVENTFD_FLAG_DEASSIGN 0x04 236 #define ACRN_IOEVENTFD_FLAG_ASYNCIO 0x08 237 /** file descriptor of the eventfd of this ioeventfd */ 238 int32_t fd; 239 /** flag for ioeventfd ioctl */ 240 uint32_t flags; 241 /** base address to be monitored */ 242 uint64_t addr; 243 /** address length */ 244 uint32_t len; 245 uint32_t reserved; 246 /** data to be matched */ 247 uint64_t data; 248 }; 249 250 struct acrn_irqfd { 251 #define ACRN_IRQFD_FLAG_DEASSIGN 0x01 252 /** file descriptor of the eventfd of this irqfd */ 253 int32_t fd; 254 /** flag for irqfd ioctl */ 255 uint32_t flags; 256 /** MSI interrupt to be injected */ 257 struct acrn_msi_entry msi; 258 }; 259 260 #endif /* VHM_IOCTL_DEFS_H */ 261