1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef UART16550_H 8 #define UART16550_H 9 10 /* Register / bit definitions for 16c550 uart */ 11 /*receive buffer register | base+00h, dlab=0b r*/ 12 #define UART16550_RBR 0x00U 13 /*transmit holding register | base+00h, dlab=0b w*/ 14 #define UART16550_THR 0x00U 15 /*divisor least significant byte | base+00h, dlab=1b rw*/ 16 #define UART16550_DLL 0x00U 17 /*interrupt enable register | base+01h, dlab=0b rw*/ 18 #define UART16550_IER 0x01U 19 /*divisor most significant byte | base+01h, dlab=1b rw*/ 20 #define UART16550_DLM 0x01U 21 /*interrupt identification register | base+02h, dlab=0b r*/ 22 #define UART16550_IIR 0x02U 23 /*fifo control register | base+02h, dlab=0b w*/ 24 #define UART16550_FCR 0x02U 25 /*line control register | base+03h, dlab=xb rw*/ 26 #define UART16550_LCR 0x03U 27 /*modem control register, only uart0 | base+04h, dlab=xb rw*/ 28 #define UART16550_MCR 0x04U 29 /*line status register | base+05h, dlab=xb r*/ 30 #define UART16550_LSR 0x05U 31 /*modem status register, only uart0 | base+06h, dlab=xb r*/ 32 #define UART16550_MSR 0x06U 33 /*scratch pad register | base+07h, dlab=xb rw*/ 34 #define UART16550_SCR 0x07U 35 36 /* value definitions for IIR */ 37 #define IIR_FIFO_MASK 0xc0U /* set if FIFOs are enabled */ 38 #define IIR_RXTOUT 0x0cU 39 #define IER_EMSC 0x08U 40 #define IIR_RLS 0x06U 41 #define IIR_RXRDY 0x04U 42 #define IIR_TXRDY 0x02U 43 #define IIR_NOPEND 0x01U 44 #define IIR_MLSC 0x00U 45 46 #define IER_EDSSI (0x0008U) 47 /*enable/disable modem status interrupt*/ 48 #define IER_ELSI (0x0004U) 49 /*enable/disable receive data error interrupt*/ 50 #define IER_ETBEI (0x0002U) 51 /*enable/disable transmit data write request interrupt*/ 52 #define IER_ERBFI (0x0001U) 53 /*enable/disable receive data read request interrupt*/ 54 55 /* definition for LCR */ 56 #define LCR_DLAB (1U << 7U) /*DLAB THR/RBR&IER or DLL&DLM= Bit 7*/ 57 #define LCR_SB (1U << 6U) /*break control on/off= Bit 6*/ 58 #define LCR_SP (1U << 5U) /*Specifies the operation of parity bit*/ 59 #define LCR_EPS (1U << 4U) /*Specifies the logic of a parity bit*/ 60 #define LCR_PEN (1U << 3U) /*Specifies whether to add a parity bit*/ 61 #define LCR_STB (1U << 2U) /*stop bit length*/ 62 #define LCR_WL8 (0x03U) /*number of bits of serial data*/ 63 #define LCR_WL7 (0x02U) /*number of bits of serial data*/ 64 #define LCR_WL6 (0x01U) /*number of bits of serial data*/ 65 #define LCR_WL5 (0x00U) /*number of bits of serial data*/ 66 #define LCR_PARITY_ODD (LCR_PEN) 67 #define LCR_PARITY_NONE 0x0U 68 #define LCR_PARITY_EVEN (LCR_PEN | LCR_EPS) 69 #define LCR_NB_STOP_BITS_1 0x0U 70 #define LCR_NB_STOP_BITS_2 (LCR_STB) 71 72 /* bit definitions for LSR */ 73 /* at least one error in data within fifo */ 74 #define LSR_ERR (1U << 7U) 75 /* Transmit data Present */ 76 #define LSR_TEMT (1U << 6U) 77 /* Transmit data write request present */ 78 #define LSR_THRE (1U << 5U) 79 /* Break interrupt data Present */ 80 #define LSR_BI (1U << 4U) 81 /* Framing Error Occurred */ 82 #define LSR_FE (1U << 3U) 83 /* Parity Error Occurred */ 84 #define LSR_PE (1U << 2U) 85 /* Overrun error */ 86 #define LSR_OE (1U << 1U) 87 /* Readable received data is present */ 88 #define LSR_DR (1U << 0U) 89 90 /* definition for MCR */ 91 #define MCR_PRESCALE (1U << 7U) /* only available on 16650 up */ 92 #define MCR_LOOPBACK (1U << 4U) 93 #define MCR_IE (1U << 3U) 94 #define MCR_IENABLE MCR_IE 95 #define MCR_DRS (1U << 2U) 96 #define MCR_RTS (1U << 1U) /* Request to Send */ 97 #define MCR_DTR (1U << 0U) /* Data Terminal Ready */ 98 99 /* defifor MSR */ 100 #define MSR_DCD (1U << 7U) 101 #define MSR_RI (1U << 6U) 102 #define MSR_DSR (1U << 5U) 103 #define MSR_CTS (1U << 4U) 104 #define MSR_DDCD (1U << 3U) 105 #define MSR_TERI (1U << 2U) 106 #define MSR_DDSR (1U << 1U) 107 #define MSR_DCTS (1U << 0U) 108 109 #define MCR_OUT2 (1U << 3U) 110 #define MCR_OUT1 (1U << 2U) 111 112 #define MSR_DELTA_MASK 0x0FU 113 114 /* definition for FCR */ 115 #define FCR_RX_MASK 0xc0U 116 #define FCR_DMA (1U << 3U) 117 #define FCR_TFR (1U << 2U) /* Reset Transmit Fifo */ 118 #define FCR_RFR (1U << 1U) /* Reset Receive Fifo */ 119 #define FCR_FIFOE (1U << 0U) /* Fifo Enable */ 120 121 #define UART_IER_DISABLE_ALL 0x00000000U 122 123 #define BAUD_9600 9600U 124 #define BAUD_115200 115200U 125 #define BAUD_460800 460800U 126 127 /* UART oscillator clock */ 128 #define UART_CLOCK_RATE 1843200U /* 1.8432 MHz */ 129 130 enum serial_dev_type { 131 INVALID, 132 PIO, 133 PCI, 134 MMIO, 135 }; 136 137 void uart16550_init(bool early_boot); 138 char uart16550_getc(void); 139 size_t uart16550_puts(const char *buf, uint32_t len); 140 void uart16550_set_property(bool enabled, enum serial_dev_type uart_type, uint64_t base_addr); 141 bool is_pci_dbg_uart(union pci_bdf bdf_value); 142 bool get_pio_dbg_uart_cfg(uint16_t *pio_address, uint32_t *nbytes); 143 144 #endif /* !UART16550_H */ 145