1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2011 NetApp, Inc.
4 * Copyright (c) 2018-2022 Intel Corporation.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #ifndef PCI_H_
31 #define PCI_H_
32
33 #include <list.h>
34
35 /*
36 * PCIM_xxx: mask to locate subfield in register
37 * PCIR_xxx: config register offset
38 * PCIC_xxx: device class
39 * PCIS_xxx: device subclass
40 * PCIP_xxx: device programming interface
41 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
42 * PCID_xxx: device ID
43 * PCIY_xxx: capability identification number
44 * PCIZ_xxx: extended capability identification number
45 */
46
47 #define PCI_CFG_HEADER_LENGTH 0x40U
48
49 /* some PCI bus constants */
50 #define PCI_BUSMAX 0xFFU
51 #define PCI_SLOTMAX 0x1FU
52 #define PCI_FUNCMAX 0x7U
53 #define PCI_BAR_COUNT 0x6U
54 #define PCI_REGMASK 0xFCU
55
56 #define PCI_CONFIG_SPACE_SIZE 0x100U
57 #define PCIE_CONFIG_SPACE_SIZE 0x1000U
58 #define PCI_MMCONFIG_SIZE 0x10000000U
59
60 /* I/O ports */
61 #define PCI_CONFIG_ADDR 0xCF8U
62 #define PCI_CONFIG_DATA 0xCFCU
63
64 #define PCI_CFG_ENABLE 0x80000000U
65
66 /* PCI config header registers for all devices */
67 #define PCIR_VENDOR 0x00U
68 #define PCIR_DEVICE 0x02U
69 #define PCIR_COMMAND 0x04U
70 #define PCIM_CMD_PORTEN 0x01U
71 #define PCIM_CMD_MEMEN 0x02U
72 #define PCIM_CMD_BUSEN 0x04U
73 #define PCIM_CMD_INTxDIS 0x400U
74 #define PCIR_STATUS 0x06U
75 #define PCIM_STATUS_CAPPRESENT 0x0010U
76 #define PCIR_REVID 0x08U
77 #define PCIR_CLASS_CODE 0x09U
78 #define PCIR_SUBCLASS 0x0AU
79 #define PCIR_CLASS 0x0BU
80 #define PCIR_HDRTYPE 0x0EU
81 #define PCIM_HDRTYPE 0x7FU
82 #define PCIM_HDRTYPE_NORMAL 0x00U
83 #define PCIM_HDRTYPE_BRIDGE 0x01U
84 #define PCIM_HDRTYPE_CARDBUS 0x02U
85 #define PCIM_MFDEV 0x80U
86 #define PCIR_BARS 0x10U
87 #define PCIM_BAR_SPACE 0x01U
88 #define PCIM_BAR_IO_SPACE 0x01U
89 #define PCIM_BAR_MEM_TYPE 0x06U
90 #define PCIM_BAR_MEM_32 0x00U
91 #define PCIM_BAR_MEM_1MB 0x02U
92 #define PCIM_BAR_MEM_64 0x04U
93 #define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
94 #define PCIV_SUB_VENDOR_ID 0x2CU
95 #define PCIV_SUB_SYSTEM_ID 0x2EU
96 #define PCIR_BIOS 0x30U
97 #define PCIR_CAP_PTR 0x34U
98 #define PCIR_CAP_PTR_CARDBUS 0x14U
99 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
100 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
101 #define PCIR_INTERRUPT_LINE 0x3cU
102 #define PCIR_INTERRUPT_PIN 0x3dU
103
104 #define PCIC_SIMPLECOMM 0x07U
105 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
106 #define PCIR_PRIBUS_1 0x18U
107 #define PCIR_SECBUS_1 0x19U
108 #define PCIR_SUBBUS_1 0x1AU
109 #define PCIR_IO_BASE 0x1CU
110 #define PCIR_IO_LIMIT 0x1DU
111 #define PCIR_MEM_BASE 0x20U
112 #define PCIR_IO_BASE_UPPER_16 0x30U
113 #define PCIR_SECSTATUS_LINE_MASK 0xFFFF0000U
114
115 /* Capability Register Offsets */
116 #define PCICAP_ID 0x0U
117 #define PCICAP_NEXTPTR 0x1U
118 #define PCICAP_EXP_CAP 0x2U
119
120 /* Capability Identification Numbers */
121 #define PCIY_MSI 0x05U
122 #define PCIY_MSIX 0x11U
123
124 /* PCIe Extended Capability*/
125 #define PCI_ECAP_BASE_PTR 0x100U
126 #define PCI_ECAP_ID(hdr) ((uint32_t)((hdr) & 0xFFFFU))
127 #define PCI_ECAP_NEXT(hdr) ((uint32_t)(((hdr) >> 20U) & 0xFFCU))
128 #define PCIZ_SRIOV 0x10U
129 #define PCIZ_PTM 0x1fU
130
131 /* SRIOV Definitions */
132 #define PCI_SRIOV_CAP_LEN 0x40U
133 #define PCIR_SRIOV_CONTROL 0x8U
134 #define PCIR_SRIOV_TOTAL_VFS 0xEU
135 #define PCIR_SRIOV_NUMVFS 0x10U
136 #define PCIR_SRIOV_FST_VF_OFF 0x14U
137 #define PCIR_SRIOV_VF_STRIDE 0x16U
138 #define PCIR_SRIOV_VF_DEV_ID 0x1AU
139 #define PCIR_SRIOV_VF_BAR_OFF 0x24U
140 #define PCIM_SRIOV_VF_ENABLE 0x1U
141
142 /* PTM Definitions */
143 #define PCI_PTM_CAP_LEN 0x04U
144 #define PCIR_PTM_CAP 0x04U
145 #define PCIM_PTM_CAP_ROOT_CAPABLE 0x4U
146 #define PCIM_PTM_GRANULARITY_MASK 0xFF00U
147 #define PCIR_PTM_CTRL 0x08U
148 #define PCIM_PTM_CTRL_ENABLED 0x1U
149 #define PCIM_PTM_CTRL_ROOT_SELECTED 0x2U
150
151 /* PCI Message Signalled Interrupts (MSI) */
152 #define PCIR_MSI_CTRL 0x02U
153 #define PCIM_MSICTRL_64BIT 0x80U
154 #define PCIM_MSICTRL_MSI_ENABLE 0x01U
155 #define PCIR_MSI_ADDR 0x4U
156 #define PCIR_MSI_ADDR_HIGH 0x8U
157 #define PCIR_MSI_DATA 0x8U
158 #define PCIR_MSI_DATA_64BIT 0xCU
159 #define PCIR_MSI_MASK 0x10U
160 #define PCIM_MSICTRL_MMC_MASK 0x000EU
161 #define PCIM_MSICTRL_MME_MASK 0x0070U
162
163 /* PCI device class */
164 #define PCIC_BRIDGE 0x06U
165 #define PCIS_BRIDGE_HOST 0x00U
166
167 /* PCI device subclass */
168 #define PCIS_BRIDGE_PCI 0x04U
169
170 /* MSI-X definitions */
171 #define PCIR_MSIX_CTRL 0x2U
172 #define PCIR_MSIX_TABLE 0x4U
173 #define PCIR_MSIX_PBA 0x8U
174
175 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000U
176 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000U
177 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FFU
178 #define PCIM_MSIX_BIR_MASK 0x7U
179 #define PCIM_MSIX_VCTRL_MASK 0x1U
180
181 #define MSIX_CAPLEN 12U
182 #define MSIX_TABLE_ENTRY_SIZE 16U
183
184 /* PCI Power Management Capability */
185 #define PCIY_PMC 0x01U
186 /* Power Management Control/Status Register */
187 #define PCIR_PMCSR 0x04U
188 #define PCIM_PMCSR_NO_SOFT_RST (0x1U << 3U)
189
190 /* PCI Express Capability */
191 #define PCIY_PCIE 0x10U
192 #define PCIR_PCIE_DEVCAP 0x04U
193 #define PCIR_PCIE_DEVCTRL 0x08U
194 #define PCIM_PCIE_DEV_CTRL_MAX_PAYLOAD 0x00E0U
195 #define PCIM_PCIE_FLRCAP (0x1U << 28U)
196 #define PCIM_PCIE_FLR (0x1U << 15U)
197
198 /* PCI Express Device Type definitions */
199 #define PCIER_FLAGS 0x2U
200 #define PCIEM_FLAGS_TYPE 0x00F0U
201 #define PCIEM_TYPE_ENDPOINT 0x0000U
202 #define PCIEM_TYPE_ROOTPORT 0x0004U
203 #define PCIEM_TYPE_ROOT_INT_EP 0x0009U
204
205 #define PCIR_PCIE_DEVCAP2 0x24U
206 #define PCIM_PCIE_DEVCAP2_ARI (0x1U << 5U)
207 #define PCIR_PCIE_DEVCTL2 0x28U
208 #define PCIM_PCIE_DEVCTL2_ARI (0x1U << 5U)
209
210 /* Conventional PCI Advanced Features Capability */
211 #define PCIY_AF 0x13U
212 #define PCIM_AF_FLR_CAP (0x1U << 25U)
213 #define PCIR_AF_CTRL 0x4U
214 #define PCIM_AF_FLR 0x1U
215
216 #define PCI_STD_NUM_BARS 6U
217
218 union pci_bdf {
219 uint16_t value;
220 struct {
221 uint8_t f : 3; /* BITs 0-2 */
222 uint8_t d : 5; /* BITs 3-7 */
223 uint8_t b; /* BITs 8-15 */
224 } bits;
225 struct {
226 uint8_t devfun; /* BITs 0-7 */
227 uint8_t bus; /* BITs 8-15 */
228 } fields;
229 };
230
231 /*
232 * The next data structure is to reflect the format of PCI BAR base on the PCI sepc.
233 */
234
235 union pci_bar_type {
236 uint32_t bits;
237 struct {
238 uint32_t indicator :1; /* BITs[0], mapped to I/O space if read as 1 */
239 uint32_t reserved :1; /* BITs[1], reserved and must be "0" per spec. */
240 uint32_t reserved2 : 30;
241 } io_space;
242 struct {
243 uint32_t indicator :1; /* BITs[0], mapped to memory space if read as 0 */
244 uint32_t mem_type :2; /* BITs[1:2], 32-bit address if read as 00b, 64-bit address as 01b */
245 uint32_t prefetchable :1; /* BITs[3], set to 1b if the data is prefetchable and set to 0b otherwise */
246 uint32_t reserved2 : 28;
247 } mem_space;
248 };
249
250 struct pci_mmcfg_region {
251 uint64_t address; /* Base address, processor-relative */
252 uint16_t pci_segment; /* PCI segment group number */
253 uint8_t start_bus; /* Starting PCI Bus number */
254 uint8_t end_bus; /* Final PCI Bus number */
255 } __packed;
256
257 /* Basic MSIX capability info */
258 struct pci_msix_cap {
259 uint32_t capoff;
260 uint32_t caplen;
261 uint8_t table_bar;
262 uint32_t table_offset;
263 uint32_t table_count;
264 uint8_t cap[MSIX_CAPLEN];
265 };
266
267 struct pci_sriov_cap {
268 uint32_t capoff;
269 uint32_t caplen;
270 uint32_t pre_pos;
271 bool hide_sriov;
272 };
273
274 /* PCI BAR size is detected at run time. We don't want to re-detect it to avoid malfunction of
275 * the device. We have record physical bar values, we need to record size_mask.
276 */
277 struct pci_bar_resource {
278 uint32_t phy_bar; /* the origional raw data read from physical BAR */
279 uint32_t size_mask; /* read value of physical BAR after write 0xffffffff */
280 };
281
282 struct pci_pdev {
283 uint8_t hdr_type;
284 uint8_t base_class;
285 uint8_t sub_class;
286
287 /* IOMMU responsible for DMA and Interrupt Remapping for this device */
288 uint32_t drhd_index;
289 /* Used for vMSI-x on MSI emulation */
290 uint16_t irte_start;
291 uint16_t irte_count;
292
293 /* The bar info of the physical PCI device. */
294 uint32_t nr_bars; /* 6 for normal device, 2 for bridge, 1 for cardbus */
295 struct pci_bar_resource bars[PCI_STD_NUM_BARS]; /* For common bar resource recording */
296
297 /* The bus/device/function triple of the physical PCI device. */
298 union pci_bdf bdf;
299
300 uint32_t msi_capoff;
301 uint32_t pcie_capoff;
302
303 struct pci_msix_cap msix;
304 struct pci_sriov_cap sriov;
305
306 bool has_pm_reset;
307 bool has_flr;
308 bool has_af_flr;
309 struct hlist_node link;
310 };
311
312 struct pci_cfg_ops {
313 uint32_t (*pci_read_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
314 void (*pci_write_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
315 };
316
is_host_bridge(const struct pci_pdev * pdev)317 static inline bool is_host_bridge(const struct pci_pdev *pdev)
318 {
319 return (pdev->base_class == PCIC_BRIDGE) && (pdev->sub_class == PCIS_BRIDGE_HOST);
320 }
321
is_bridge(const struct pci_pdev * pdev)322 static inline bool is_bridge(const struct pci_pdev *pdev)
323 {
324 return ((pdev->hdr_type & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE);
325 }
326
pci_bar_offset(uint32_t idx)327 static inline uint32_t pci_bar_offset(uint32_t idx)
328 {
329 return PCIR_BARS + (idx << 2U);
330 }
331
pci_bar_index(uint32_t offset)332 static inline uint32_t pci_bar_index(uint32_t offset)
333 {
334 return (offset - PCIR_BARS) >> 2U;
335 }
336
is_bar_offset(uint32_t nr_bars,uint32_t offset)337 static inline bool is_bar_offset(uint32_t nr_bars, uint32_t offset)
338 {
339 bool ret;
340
341 if ((offset >= pci_bar_offset(0U))
342 && (offset < pci_bar_offset(nr_bars))) {
343 ret = true;
344 } else {
345 ret = false;
346 }
347
348 return ret;
349 }
350
bdf_is_equal(union pci_bdf a,union pci_bdf b)351 static inline bool bdf_is_equal(union pci_bdf a, union pci_bdf b)
352 {
353 return (a.value == b.value);
354 }
355
get_pci_mmcfg_size(struct pci_mmcfg_region * pci_mmcfg)356 static inline uint64_t get_pci_mmcfg_size(struct pci_mmcfg_region *pci_mmcfg)
357 {
358 return 0x100000UL * (pci_mmcfg->end_bus - pci_mmcfg->start_bus + 1U);
359 }
360
361 #ifdef CONFIG_ACPI_PARSE_ENABLED
362 void set_mmcfg_region(struct pci_mmcfg_region *region);
363 #endif
364 struct pci_mmcfg_region *get_mmcfg_region(void);
365
366 struct pci_pdev *pci_init_pdev(union pci_bdf pbdf, uint32_t drhd_index);
367 uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
368 void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
369 void enable_disable_pci_intx(union pci_bdf bdf, bool enable);
370
371 bool is_hv_owned_pdev(union pci_bdf pbdf);
372 uint32_t get_hv_owned_pdev_num(void);
373 const struct pci_pdev **get_hv_owned_pdevs(void);
374 /*
375 * @brief Walks the PCI heirarchy and initializes array of pci_pdev structs
376 * Uses DRHD info from ACPI DMAR tables to cover the endpoints and
377 * bridges along with their hierarchy captured in the device scope entries
378 * Walks through rest of the devices starting at bus 0 and thru PCI_BUSMAX
379 */
380 void init_pci_pdev_list(void);
381
382 /* @brief: Find the DRHD index corresponding to a PCI device
383 * Runs through the pci_pdevs and returns the value in drhd_idx
384 * member from pdev strucutre that matches matches B:D.F
385 *
386 * @pbdf[in] B:D.F of a PCI device
387 *
388 * @return if there is a matching pbdf in pci_pdevs, pdev->drhd_idx, else -1U
389 */
390 uint32_t pci_lookup_drhd_for_pbdf(uint16_t pbdf);
391
is_pci_vendor_valid(uint32_t vendor_id)392 static inline bool is_pci_vendor_valid(uint32_t vendor_id)
393 {
394 return !((vendor_id == 0xFFFFFFFFU) || (vendor_id == 0U) ||
395 (vendor_id == 0xFFFF0000U) || (vendor_id == 0xFFFFU));
396 }
397
is_pci_cfg_multifunction(uint8_t header_type)398 static inline bool is_pci_cfg_multifunction(uint8_t header_type)
399 {
400 return ((header_type != 0xffU) && ((header_type & PCIM_MFDEV) == PCIM_MFDEV));
401 }
402
pci_is_valid_access_offset(uint32_t offset,uint32_t bytes)403 static inline bool pci_is_valid_access_offset(uint32_t offset, uint32_t bytes)
404 {
405 return ((offset & (bytes - 1U)) == 0U);
406 }
407
pci_is_valid_access_byte(uint32_t bytes)408 static inline bool pci_is_valid_access_byte(uint32_t bytes)
409 {
410 return ((bytes == 1U) || (bytes == 2U) || (bytes == 4U));
411 }
412
pci_is_valid_access(uint32_t offset,uint32_t bytes)413 static inline bool pci_is_valid_access(uint32_t offset, uint32_t bytes)
414 {
415 return (pci_is_valid_access_byte(bytes) && pci_is_valid_access_offset(offset, bytes));
416 }
417
418 bool is_plat_hidden_pdev(union pci_bdf bdf);
419 bool pdev_need_bar_restore(const struct pci_pdev *pdev);
420 void pdev_restore_bar(const struct pci_pdev *pdev);
421 void pci_switch_to_mmio_cfg_ops(void);
422 void reserve_vmsix_on_msi_irtes(struct pci_pdev *pdev);
423
424 #endif /* PCI_H_ */
425