1 /* 2 * hypercall definition 3 * 4 * Copyright (C) 2017-2022 Intel Corporation. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 /** 10 * @file acrn_hv_defs.h 11 * 12 * @brief acrn data structure for hypercall 13 */ 14 15 #ifndef ACRN_HV_DEFS_H 16 #define ACRN_HV_DEFS_H 17 18 /* 19 * Common structures for HV/HSM 20 */ 21 22 #define BASE_HC_ID(x, y) (((x)<<24U)|(y)) 23 #define HC_IDX(id) ((id)&(0xFFUL)) 24 25 #define HC_ID 0x80UL 26 27 /* general */ 28 #define HC_ID_GEN_BASE 0x0UL 29 #define HC_GET_API_VERSION BASE_HC_ID(HC_ID, HC_ID_GEN_BASE + 0x00UL) 30 #define HC_SERVICE_VM_OFFLINE_CPU BASE_HC_ID(HC_ID, HC_ID_GEN_BASE + 0x01UL) 31 #define HC_SET_CALLBACK_VECTOR BASE_HC_ID(HC_ID, HC_ID_GEN_BASE + 0x02UL) 32 33 /* VM management */ 34 #define HC_ID_VM_BASE 0x10UL 35 #define HC_CREATE_VM BASE_HC_ID(HC_ID, HC_ID_VM_BASE + 0x00UL) 36 #define HC_DESTROY_VM BASE_HC_ID(HC_ID, HC_ID_VM_BASE + 0x01UL) 37 #define HC_START_VM BASE_HC_ID(HC_ID, HC_ID_VM_BASE + 0x02UL) 38 #define HC_PAUSE_VM BASE_HC_ID(HC_ID, HC_ID_VM_BASE + 0x03UL) 39 #define HC_CREATE_VCPU BASE_HC_ID(HC_ID, HC_ID_VM_BASE + 0x04UL) 40 #define HC_RESET_VM BASE_HC_ID(HC_ID, HC_ID_VM_BASE + 0x05UL) 41 #define HC_SET_VCPU_REGS BASE_HC_ID(HC_ID, HC_ID_VM_BASE + 0x06UL) 42 43 /* IRQ and Interrupts */ 44 #define HC_ID_IRQ_BASE 0x20UL 45 #define HC_INJECT_MSI BASE_HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x03UL) 46 #define HC_VM_INTR_MONITOR BASE_HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x04UL) 47 #define HC_SET_IRQLINE BASE_HC_ID(HC_ID, HC_ID_IRQ_BASE + 0x05UL) 48 49 /* DM ioreq management */ 50 #define HC_ID_IOREQ_BASE 0x30UL 51 #define HC_SET_IOREQ_BUFFER BASE_HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x00UL) 52 #define HC_NOTIFY_REQUEST_FINISH BASE_HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x01UL) 53 #define HC_ASYNCIO_ASSIGN BASE_HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x02UL) 54 #define HC_ASYNCIO_DEASSIGN BASE_HC_ID(HC_ID, HC_ID_IOREQ_BASE + 0x03UL) 55 56 57 /* Guest memory management */ 58 #define HC_ID_MEM_BASE 0x40UL 59 #define HC_VM_GPA2HPA BASE_HC_ID(HC_ID, HC_ID_MEM_BASE + 0x01UL) 60 #define HC_VM_SET_MEMORY_REGIONS BASE_HC_ID(HC_ID, HC_ID_MEM_BASE + 0x02UL) 61 #define HC_VM_WRITE_PROTECT_PAGE BASE_HC_ID(HC_ID, HC_ID_MEM_BASE + 0x03UL) 62 #define HC_SETUP_SBUF BASE_HC_ID(HC_ID, HC_ID_MEM_BASE + 0x04UL) 63 64 /* PCI assignment*/ 65 #define HC_ID_PCI_BASE 0x50UL 66 #define HC_ASSIGN_PTDEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x00UL) 67 #define HC_DEASSIGN_PTDEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x01UL) 68 #define HC_VM_PCI_MSIX_REMAP BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x02UL) 69 #define HC_SET_PTDEV_INTR_INFO BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x03UL) 70 #define HC_RESET_PTDEV_INTR_INFO BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x04UL) 71 #define HC_ASSIGN_PCIDEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x05UL) 72 #define HC_DEASSIGN_PCIDEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x06UL) 73 #define HC_ASSIGN_MMIODEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x07UL) 74 #define HC_DEASSIGN_MMIODEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x08UL) 75 #define HC_ADD_VDEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x09UL) 76 #define HC_REMOVE_VDEV BASE_HC_ID(HC_ID, HC_ID_PCI_BASE + 0x0AUL) 77 78 /* DEBUG */ 79 #define HC_ID_DBG_BASE 0x60UL 80 #define HC_SETUP_HV_NPK_LOG BASE_HC_ID(HC_ID, HC_ID_DBG_BASE + 0x01UL) 81 #define HC_PROFILING_OPS BASE_HC_ID(HC_ID, HC_ID_DBG_BASE + 0x02UL) 82 #define HC_GET_HW_INFO BASE_HC_ID(HC_ID, HC_ID_DBG_BASE + 0x03UL) 83 84 /* Trusty */ 85 #define HC_ID_TRUSTY_BASE 0x70UL 86 #define HC_INITIALIZE_TRUSTY BASE_HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x00UL) 87 #define HC_WORLD_SWITCH BASE_HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x01UL) 88 #define HC_SAVE_RESTORE_SWORLD_CTX BASE_HC_ID(HC_ID, HC_ID_TRUSTY_BASE + 0x02UL) 89 90 /* Power management */ 91 #define HC_ID_PM_BASE 0x80UL 92 #define HC_PM_GET_CPU_STATE BASE_HC_ID(HC_ID, HC_ID_PM_BASE + 0x00UL) 93 94 /* X86 TEE */ 95 #define HC_ID_TEE_BASE 0x90UL 96 #define HC_TEE_VCPU_BOOT_DONE BASE_HC_ID(HC_ID, HC_ID_TEE_BASE + 0x00UL) 97 #define HC_SWITCH_EE BASE_HC_ID(HC_ID, HC_ID_TEE_BASE + 0x01UL) 98 99 #define ACRN_INVALID_VMID (0xffffU) 100 #define ACRN_INVALID_HPA (~0UL) 101 102 /* Generic memory attributes */ 103 #define MEM_ACCESS_READ 0x00000001U 104 #define MEM_ACCESS_WRITE 0x00000002U 105 #define MEM_ACCESS_EXEC 0x00000004U 106 #define MEM_ACCESS_RWX (MEM_ACCESS_READ | MEM_ACCESS_WRITE | \ 107 MEM_ACCESS_EXEC) 108 #define MEM_ACCESS_RIGHT_MASK 0x00000007U 109 #define MEM_TYPE_WB 0x00000040U 110 #define MEM_TYPE_WT 0x00000080U 111 #define MEM_TYPE_UC 0x00000100U 112 #define MEM_TYPE_WC 0x00000200U 113 #define MEM_TYPE_WP 0x00000400U 114 #define MEM_TYPE_MASK 0x000007C0U 115 116 /** 117 * @brief Hypercall 118 * 119 * @defgroup acrn_hypercall ACRN Hypercall 120 * @{ 121 */ 122 123 /** 124 * @brief Info to set guest memory region mapping 125 * 126 * the parameter for HC_VM_SET_MEMORY_REGION hypercall 127 */ 128 struct vm_memory_region { 129 #define MR_ADD 0U 130 #define MR_DEL 2U 131 #define MR_MODIFY 3U 132 /** set memory region type: MR_ADD or MAP_DEL */ 133 uint32_t type; 134 135 /** memory attributes: memory type + RWX access right */ 136 uint32_t prot; 137 138 /** the beginning guest physical address of the memory reion*/ 139 uint64_t gpa; 140 141 /** Service VM's guest physcial address which gpa will be mapped to */ 142 uint64_t service_vm_gpa; 143 144 /** size of the memory region */ 145 uint64_t size; 146 } __aligned(8); 147 148 /** 149 * set multi memory regions, used for HC_VM_SET_MEMORY_REGIONS 150 */ 151 struct set_regions { 152 /** vmid for this hypercall */ 153 uint16_t vmid; 154 155 /** Reserved */ 156 uint16_t reserved0; 157 158 /** Reserved */ 159 uint32_t reserved1; 160 161 /** memory region numbers */ 162 uint32_t mr_num; 163 164 /** the gpa of regions buffer, point to the regions array: 165 * struct vm_memory_region regions[mr_num] 166 * the max buffer size is one page. 167 */ 168 uint64_t regions_gpa; 169 } __aligned(8); 170 171 /** 172 * @brief Info to change guest one page write protect permission 173 * 174 * the parameter for HC_VM_WRITE_PROTECT_PAGE hypercall 175 */ 176 struct wp_data { 177 /** set page write protect permission. 178 * ture: set the wp; flase: clear the wp 179 */ 180 uint8_t set; 181 182 /** Reserved */ 183 uint64_t pad:56; 184 185 /** the guest physical address of the page to change */ 186 uint64_t gpa; 187 } __aligned(8); 188 189 /** 190 * Setup parameter for share buffer, used for HC_SETUP_SBUF hypercall 191 */ 192 struct acrn_sbuf_param { 193 /** sbuf cpu id */ 194 uint16_t cpu_id; 195 196 /** Reserved */ 197 uint16_t reserved; 198 199 /** sbuf id */ 200 uint32_t sbuf_id; 201 202 /** sbuf's guest physical address */ 203 uint64_t gpa; 204 } __aligned(8); 205 206 /** 207 * @brief Info to setup the hypervisor NPK log 208 * 209 * the parameter for HC_SETUP_HV_NPK_LOG hypercall 210 */ 211 struct hv_npk_log_param { 212 /** the setup command for the hypervisor NPK log */ 213 uint16_t cmd; 214 215 /** the setup result for the hypervisor NPK log */ 216 uint16_t res; 217 218 /** the loglevel for the hypervisor NPK log */ 219 uint16_t loglevel; 220 221 /** Reserved */ 222 uint16_t reserved; 223 224 /** the MMIO address for the hypervisor NPK log */ 225 uint64_t mmio_addr; 226 } __aligned(8); 227 228 /** 229 * the parameter for HC_GET_HW_INFO hypercall 230 */ 231 struct acrn_hw_info { 232 uint16_t cpu_num; /* Physical CPU number */ 233 uint16_t reserved[3]; 234 } __aligned(8); 235 236 /** 237 * Gpa to hpa translation parameter, used for HC_VM_GPA2HPA hypercall 238 */ 239 struct vm_gpa2hpa { 240 /** gpa to do translation */ 241 uint64_t gpa; 242 243 /** hpa to return after translation */ 244 uint64_t hpa; 245 } __aligned(8); 246 247 /** 248 * Intr mapping info per ptdev, the parameter for HC_SET_PTDEV_INTR_INFO 249 * hypercall 250 */ 251 struct hc_ptdev_irq { 252 #define IRQ_INTX 0U 253 #define IRQ_MSI 1U 254 #define IRQ_MSIX 2U 255 /** irq mapping type: INTX or MSI */ 256 uint32_t type; 257 258 /** virtual BDF of the ptdev */ 259 uint16_t virt_bdf; 260 261 /** physical BDF of the ptdev */ 262 uint16_t phys_bdf; 263 264 /** INTX remapping info */ 265 struct intx_info { 266 /** virtual IOAPIC/PIC pin */ 267 uint32_t virt_pin; 268 269 /** physical IOAPIC pin */ 270 uint32_t phys_pin; 271 272 /** is virtual pin from PIC */ 273 bool pic_pin; 274 275 /** Reserved */ 276 uint8_t reserved[3]; 277 } intx; 278 279 } __aligned(8); 280 281 /** 282 * Hypervisor api version info, return it for HC_GET_API_VERSION hypercall 283 */ 284 struct hc_api_version { 285 /** hypervisor api major version */ 286 uint32_t major_version; 287 288 /** hypervisor api minor version */ 289 uint32_t minor_version; 290 } __aligned(8); 291 292 #define ACRN_PLATFORM_LAPIC_IDS_MAX 64U 293 294 /** 295 * Trusty boot params, used for HC_INITIALIZE_TRUSTY 296 */ 297 struct trusty_boot_param { 298 /** sizeof this structure */ 299 uint32_t size_of_this_struct; 300 301 /** version of this structure */ 302 uint32_t version; 303 304 /** trusty runtime memory base address */ 305 uint32_t base_addr; 306 307 /** trusty entry point */ 308 uint32_t entry_point; 309 310 /** trusty runtime memory size */ 311 uint32_t mem_size; 312 313 /** padding */ 314 uint32_t padding; 315 316 /** trusty runtime memory base address (high 32bit) */ 317 uint32_t base_addr_high; 318 319 /** trusty entry point (high 32bit) */ 320 uint32_t entry_point_high; 321 322 /** rpmb key */ 323 uint8_t rpmb_key[64]; 324 } __aligned(8); 325 326 /** 327 * @} 328 */ 329 330 enum profiling_cmd_type { 331 PROFILING_MSR_OPS = 0U, 332 PROFILING_GET_VMINFO, 333 PROFILING_GET_VERSION, 334 PROFILING_GET_CONTROL_SWITCH, 335 PROFILING_SET_CONTROL_SWITCH, 336 PROFILING_CONFIG_PMI, 337 PROFILING_CONFIG_VMSWITCH, 338 PROFILING_GET_PCPUID, 339 PROFILING_GET_STATUS 340 }; 341 342 #endif /* ACRN_HV_DEFS_H */ 343