1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VMX_H_ 8 #define VMX_H_ 9 10 /* 16-bit control fields */ 11 #define VMX_VPID 0x00000000U 12 #define VMX_POSTED_INTR_VECTOR 0x00000002U 13 /* 16-bit guest-state fields */ 14 #define VMX_GUEST_ES_SEL 0x00000800U 15 #define VMX_GUEST_CS_SEL 0x00000802U 16 #define VMX_GUEST_SS_SEL 0x00000804U 17 #define VMX_GUEST_DS_SEL 0x00000806U 18 #define VMX_GUEST_FS_SEL 0x00000808U 19 #define VMX_GUEST_GS_SEL 0x0000080aU 20 #define VMX_GUEST_LDTR_SEL 0x0000080cU 21 #define VMX_GUEST_TR_SEL 0x0000080eU 22 #define VMX_GUEST_INTR_STATUS 0x00000810U 23 #define VMX_GUEST_PML_INDEX 0x00000812U 24 /* 16-bit host-state fields */ 25 #define VMX_HOST_ES_SEL 0x00000c00U 26 #define VMX_HOST_CS_SEL 0x00000c02U 27 #define VMX_HOST_SS_SEL 0x00000c04U 28 #define VMX_HOST_DS_SEL 0x00000c06U 29 #define VMX_HOST_FS_SEL 0x00000c08U 30 #define VMX_HOST_GS_SEL 0x00000c0aU 31 #define VMX_HOST_TR_SEL 0x00000c0cU 32 /* 64-bit control fields */ 33 #define VMX_IO_BITMAP_A_FULL 0x00002000U 34 #define VMX_IO_BITMAP_A_HIGH 0x00002001U 35 #define VMX_IO_BITMAP_B_FULL 0x00002002U 36 #define VMX_IO_BITMAP_B_HIGH 0x00002003U 37 #define VMX_MSR_BITMAP_FULL 0x00002004U 38 #define VMX_MSR_BITMAP_HIGH 0x00002005U 39 #define VMX_EXIT_MSR_STORE_ADDR_FULL 0x00002006U 40 #define VMX_EXIT_MSR_STORE_ADDR_HIGH 0x00002007U 41 #define VMX_EXIT_MSR_LOAD_ADDR_FULL 0x00002008U 42 #define VMX_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009U 43 #define VMX_ENTRY_MSR_LOAD_ADDR_FULL 0x0000200aU 44 #define VMX_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200bU 45 #define VMX_EXECUTIVE_VMCS_PTR_FULL 0x0000200cU 46 #define VMX_EXECUTIVE_VMCS_PTR_HIGH 0x0000200dU 47 #define VMX_PML_ADDR_FULL 0x0000200EU 48 #define VMX_TSC_OFFSET_FULL 0x00002010U 49 #define VMX_TSC_OFFSET_HIGH 0x00002011U 50 #define VMX_VIRTUAL_APIC_PAGE_ADDR_FULL 0x00002012U 51 #define VMX_VIRTUAL_APIC_PAGE_ADDR_HIGH 0x00002013U 52 #define VMX_APIC_ACCESS_ADDR_FULL 0x00002014U 53 #define VMX_APIC_ACCESS_ADDR_HIGH 0x00002015U 54 #define VMX_PIR_DESC_ADDR_FULL 0x00002016U 55 #define VMX_PIR_DESC_ADDR_HIGH 0x00002017U 56 #define VMX_VM_FUNCTION_CTL_FULL 0x00002018U 57 #define VMX_EPT_POINTER_FULL 0x0000201AU 58 #define VMX_EPT_POINTER_HIGH 0x0000201BU 59 #define VMX_EOI_EXIT0_FULL 0x0000201CU 60 #define VMX_EOI_EXIT0_HIGH 0x0000201DU 61 #define VMX_EOI_EXIT1_FULL 0x0000201EU 62 #define VMX_EOI_EXIT1_HIGH 0x0000201FU 63 #define VMX_EOI_EXIT2_FULL 0x00002020U 64 #define VMX_EOI_EXIT2_HIGH 0x00002021U 65 #define VMX_EOI_EXIT3_FULL 0x00002022U 66 #define VMX_EOI_EXIT3_HIGH 0x00002023U 67 #define VMX_EPT_LIST_ADDR_FULL 0x00002024U 68 #define VMX_VMREAD_BITMAP_FULL 0x00002026U 69 #define VMX_VMREAD_BITMAP_HIGH 0x00002027U 70 #define VMX_VMWRITE_BITMAP_FULL 0x00002028U 71 #define VMX_VMWRITE_BITMAP_HIGH 0x00002029U 72 73 #define VMX_VIR_EXCEPTION_INFO_FULL 0x0000202AU 74 #define VMX_XSS_EXITING_BITMAP_FULL 0x0000202CU 75 #define VMX_XSS_EXITING_BITMAP_HIGH 0x0000202DU 76 #define VMX_TSC_MULTIPLIER_FULL 0x00002032U 77 78 #define VMX_PROC_VM_EXEC_CONTROLS3_FULL 0x00002034U 79 #define VMX_PROC_VM_EXEC_CONTROLS3_HIGH 0x00002035U 80 81 /* 64-bit read-only data fields */ 82 #define VMX_GUEST_PHYSICAL_ADDR_FULL 0x00002400U 83 #define VMX_GUEST_PHYSICAL_ADDR_HIGH 0x00002401U 84 /* 64-bit guest-state fields */ 85 #define VMX_VMS_LINK_PTR_FULL 0x00002800U 86 #define VMX_VMS_LINK_PTR_HIGH 0x00002801U 87 #define VMX_GUEST_IA32_DEBUGCTL_FULL 0x00002802U 88 #define VMX_GUEST_IA32_DEBUGCTL_HIGH 0x00002803U 89 #define VMX_GUEST_IA32_PAT_FULL 0x00002804U 90 #define VMX_GUEST_IA32_PAT_HIGH 0x00002805U 91 #define VMX_GUEST_IA32_EFER_FULL 0x00002806U 92 #define VMX_GUEST_IA32_EFER_HIGH 0x00002807U 93 #define VMX_GUEST_IA32_PERF_CTL_FULL 0x00002808U 94 #define VMX_GUEST_IA32_PERF_CTL_HIGH 0x00002809U 95 #define VMX_GUEST_PDPTE0_FULL 0x0000280AU 96 #define VMX_GUEST_PDPTE0_HIGH 0x0000280BU 97 #define VMX_GUEST_PDPTE1_FULL 0x0000280CU 98 #define VMX_GUEST_PDPTE1_HIGH 0x0000280DU 99 #define VMX_GUEST_PDPTE2_FULL 0x0000280EU 100 #define VMX_GUEST_PDPTE2_HIGH 0x0000280FU 101 #define VMX_GUEST_PDPTE3_FULL 0x00002810U 102 #define VMX_GUEST_PDPTE3_HIGH 0x00002811U 103 #define VMX_GUEST_IA32_BNDCFGS_FULL 0x00002812U 104 #define VMX_GUEST_IA32_BNDCFGS_HIGH 0x00002813U 105 106 /* 64-bit host-state fields */ 107 #define VMX_HOST_IA32_PAT_FULL 0x00002C00U 108 #define VMX_HOST_IA32_PAT_HIGH 0x00002C01U 109 #define VMX_HOST_IA32_EFER_FULL 0x00002C02U 110 #define VMX_HOST_IA32_EFER_HIGH 0x00002C03U 111 #define VMX_HOST_IA32_PERF_CTL_FULL 0x00002C04U 112 #define VMX_HOST_IA32_PERF_CTL_HIGH 0x00002C05U 113 /* 32-bit control fields */ 114 #define VMX_PIN_VM_EXEC_CONTROLS 0x00004000U 115 #define VMX_PROC_VM_EXEC_CONTROLS 0x00004002U 116 #define VMX_EXCEPTION_BITMAP 0x00004004U 117 #define VMX_PF_ERROR_CODE_MASK 0x00004006U 118 #define VMX_PF_ERROR_CODE_MATCH 0x00004008U 119 #define VMX_CR3_TARGET_COUNT 0x0000400aU 120 #define VMX_EXIT_CONTROLS 0x0000400cU 121 #define VMX_EXIT_MSR_STORE_COUNT 0x0000400eU 122 #define VMX_EXIT_MSR_LOAD_COUNT 0x00004010U 123 #define VMX_ENTRY_CONTROLS 0x00004012U 124 #define VMX_ENTRY_MSR_LOAD_COUNT 0x00004014U 125 #define VMX_ENTRY_INT_INFO_FIELD 0x00004016U 126 #define VMX_ENTRY_EXCEPTION_ERROR_CODE 0x00004018U 127 #define VMX_ENTRY_INSTR_LENGTH 0x0000401aU 128 #define VMX_TPR_THRESHOLD 0x0000401cU 129 #define VMX_PROC_VM_EXEC_CONTROLS2 0x0000401EU 130 #define VMX_PLE_GAP 0x00004020U 131 #define VMX_PLE_WINDOW 0x00004022U 132 /* 32-bit read-only data fields */ 133 #define VMX_INSTR_ERROR 0x00004400U 134 #define VMX_EXIT_REASON 0x00004402U 135 #define VMX_EXIT_INT_INFO 0x00004404U 136 #define VMX_EXIT_INT_ERROR_CODE 0x00004406U 137 #define VMX_IDT_VEC_INFO_FIELD 0x00004408U 138 #define VMX_IDT_VEC_ERROR_CODE 0x0000440aU 139 #define VMX_EXIT_INSTR_LEN 0x0000440cU 140 #define VMX_INSTR_INFO 0x0000440eU 141 /* 32-bit guest-state fields */ 142 #define VMX_GUEST_ES_LIMIT 0x00004800U 143 #define VMX_GUEST_CS_LIMIT 0x00004802U 144 #define VMX_GUEST_SS_LIMIT 0x00004804U 145 #define VMX_GUEST_DS_LIMIT 0x00004806U 146 #define VMX_GUEST_FS_LIMIT 0x00004808U 147 #define VMX_GUEST_GS_LIMIT 0x0000480aU 148 #define VMX_GUEST_LDTR_LIMIT 0x0000480cU 149 #define VMX_GUEST_TR_LIMIT 0x0000480eU 150 #define VMX_GUEST_GDTR_LIMIT 0x00004810U 151 #define VMX_GUEST_IDTR_LIMIT 0x00004812U 152 #define VMX_GUEST_ES_ATTR 0x00004814U 153 #define VMX_GUEST_CS_ATTR 0x00004816U 154 #define VMX_GUEST_SS_ATTR 0x00004818U 155 #define VMX_GUEST_DS_ATTR 0x0000481aU 156 #define VMX_GUEST_FS_ATTR 0x0000481cU 157 #define VMX_GUEST_GS_ATTR 0x0000481eU 158 #define VMX_GUEST_LDTR_ATTR 0x00004820U 159 #define VMX_GUEST_TR_ATTR 0x00004822U 160 #define VMX_GUEST_INTERRUPTIBILITY_INFO 0x00004824U 161 #define VMX_GUEST_ACTIVITY_STATE 0x00004826U 162 #define VMX_GUEST_SMBASE 0x00004828U 163 #define VMX_GUEST_IA32_SYSENTER_CS 0x0000482aU 164 #define VMX_GUEST_TIMER 0x0000482EU 165 /* 32-bit host-state fields */ 166 #define VMX_HOST_IA32_SYSENTER_CS 0x00004c00U 167 /* natural-width control fields */ 168 #define VMX_CR0_GUEST_HOST_MASK 0x00006000U 169 #define VMX_CR4_GUEST_HOST_MASK 0x00006002U 170 #define VMX_CR0_READ_SHADOW 0x00006004U 171 #define VMX_CR4_READ_SHADOW 0x00006006U 172 #define VMX_CR3_TARGET_0 0x00006008U 173 #define VMX_CR3_TARGET_1 0x0000600aU 174 #define VMX_CR3_TARGET_2 0x0000600cU 175 #define VMX_CR3_TARGET_3 0x0000600eU 176 /* natural-width read-only data fields */ 177 #define VMX_EXIT_QUALIFICATION 0x00006400U 178 #define VMX_IO_RCX 0x00006402U 179 #define VMX_IO_RSI 0x00006404U 180 #define VMX_IO_RDI 0x00006406U 181 #define VMX_IO_RIP 0x00006408U 182 #define VMX_GUEST_LINEAR_ADDR 0x0000640aU 183 /* natural-width guest-state fields */ 184 #define VMX_GUEST_CR0 0x00006800U 185 #define VMX_GUEST_CR3 0x00006802U 186 #define VMX_GUEST_CR4 0x00006804U 187 #define VMX_GUEST_ES_BASE 0x00006806U 188 #define VMX_GUEST_CS_BASE 0x00006808U 189 #define VMX_GUEST_SS_BASE 0x0000680aU 190 #define VMX_GUEST_DS_BASE 0x0000680cU 191 #define VMX_GUEST_FS_BASE 0x0000680eU 192 #define VMX_GUEST_GS_BASE 0x00006810U 193 #define VMX_GUEST_LDTR_BASE 0x00006812U 194 #define VMX_GUEST_TR_BASE 0x00006814U 195 #define VMX_GUEST_GDTR_BASE 0x00006816U 196 #define VMX_GUEST_IDTR_BASE 0x00006818U 197 #define VMX_GUEST_DR7 0x0000681aU 198 #define VMX_GUEST_RSP 0x0000681cU 199 #define VMX_GUEST_RIP 0x0000681eU 200 #define VMX_GUEST_RFLAGS 0x00006820U 201 #define VMX_GUEST_PENDING_DEBUG_EXCEPT 0x00006822U 202 #define VMX_GUEST_IA32_SYSENTER_ESP 0x00006824U 203 #define VMX_GUEST_IA32_SYSENTER_EIP 0x00006826U 204 /* natural-width host-state fields */ 205 #define VMX_HOST_CR0 0x00006c00U 206 #define VMX_HOST_CR3 0x00006c02U 207 #define VMX_HOST_CR4 0x00006c04U 208 #define VMX_HOST_FS_BASE 0x00006c06U 209 #define VMX_HOST_GS_BASE 0x00006c08U 210 #define VMX_HOST_TR_BASE 0x00006c0aU 211 #define VMX_HOST_GDTR_BASE 0x00006c0cU 212 #define VMX_HOST_IDTR_BASE 0x00006c0eU 213 #define VMX_HOST_IA32_SYSENTER_ESP 0x00006c10U 214 #define VMX_HOST_IA32_SYSENTER_EIP 0x00006c12U 215 #define VMX_HOST_RSP 0x00006c14U 216 #define VMX_HOST_RIP 0x00006c16U 217 /* 218 * Basic VM exit reasons 219 */ 220 #define VMX_EXIT_REASON_EXCEPTION_OR_NMI 0x00000000U 221 #define VMX_EXIT_REASON_EXTERNAL_INTERRUPT 0x00000001U 222 #define VMX_EXIT_REASON_TRIPLE_FAULT 0x00000002U 223 #define VMX_EXIT_REASON_INIT_SIGNAL 0x00000003U 224 #define VMX_EXIT_REASON_STARTUP_IPI 0x00000004U 225 #define VMX_EXIT_REASON_IO_SMI 0x00000005U 226 #define VMX_EXIT_REASON_OTHER_SMI 0x00000006U 227 #define VMX_EXIT_REASON_INTERRUPT_WINDOW 0x00000007U 228 #define VMX_EXIT_REASON_NMI_WINDOW 0x00000008U 229 #define VMX_EXIT_REASON_TASK_SWITCH 0x00000009U 230 #define VMX_EXIT_REASON_CPUID 0x0000000AU 231 #define VMX_EXIT_REASON_GETSEC 0x0000000BU 232 #define VMX_EXIT_REASON_HLT 0x0000000CU 233 #define VMX_EXIT_REASON_INVD 0x0000000DU 234 #define VMX_EXIT_REASON_INVLPG 0x0000000EU 235 #define VMX_EXIT_REASON_RDPMC 0x0000000FU 236 #define VMX_EXIT_REASON_RDTSC 0x00000010U 237 #define VMX_EXIT_REASON_RSM 0x00000011U 238 #define VMX_EXIT_REASON_VMCALL 0x00000012U 239 #define VMX_EXIT_REASON_VMCLEAR 0x00000013U 240 #define VMX_EXIT_REASON_VMLAUNCH 0x00000014U 241 #define VMX_EXIT_REASON_VMPTRLD 0x00000015U 242 #define VMX_EXIT_REASON_VMPTRST 0x00000016U 243 #define VMX_EXIT_REASON_VMREAD 0x00000017U 244 #define VMX_EXIT_REASON_VMRESUME 0x00000018U 245 #define VMX_EXIT_REASON_VMWRITE 0x00000019U 246 #define VMX_EXIT_REASON_VMXOFF 0x0000001AU 247 #define VMX_EXIT_REASON_VMXON 0x0000001BU 248 #define VMX_EXIT_REASON_CR_ACCESS 0x0000001CU 249 #define VMX_EXIT_REASON_DR_ACCESS 0x0000001DU 250 #define VMX_EXIT_REASON_IO_INSTRUCTION 0x0000001EU 251 #define VMX_EXIT_REASON_RDMSR 0x0000001FU 252 #define VMX_EXIT_REASON_WRMSR 0x00000020U 253 #define VMX_EXIT_REASON_ENTRY_FAILURE_INVALID_GUEST_STATE 0x00000021U 254 #define VMX_EXIT_REASON_ENTRY_FAILURE_MSR_LOADING 0x00000022U 255 /* entry 0x23 (35) is missing */ 256 #define VMX_EXIT_REASON_MWAIT 0x00000024U 257 #define VMX_EXIT_REASON_MONITOR_TRAP 0x00000025U 258 /* entry 0x26 (38) is missing */ 259 #define VMX_EXIT_REASON_MONITOR 0x00000027U 260 #define VMX_EXIT_REASON_PAUSE 0x00000028U 261 #define VMX_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 0x00000029U 262 /* entry 0x2A (42) is missing */ 263 #define VMX_EXIT_REASON_TPR_BELOW_THRESHOLD 0x0000002BU 264 #define VMX_EXIT_REASON_APIC_ACCESS 0x0000002CU 265 #define VMX_EXIT_REASON_VIRTUALIZED_EOI 0x0000002DU 266 #define VMX_EXIT_REASON_GDTR_IDTR_ACCESS 0x0000002EU 267 #define VMX_EXIT_REASON_LDTR_TR_ACCESS 0x0000002FU 268 #define VMX_EXIT_REASON_EPT_VIOLATION 0x00000030U 269 #define VMX_EXIT_REASON_EPT_MISCONFIGURATION 0x00000031U 270 #define VMX_EXIT_REASON_INVEPT 0x00000032U 271 #define VMX_EXIT_REASON_RDTSCP 0x00000033U 272 #define VMX_EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED 0x00000034U 273 #define VMX_EXIT_REASON_INVVPID 0x00000035U 274 #define VMX_EXIT_REASON_WBINVD 0x00000036U 275 #define VMX_EXIT_REASON_XSETBV 0x00000037U 276 #define VMX_EXIT_REASON_APIC_WRITE 0x00000038U 277 #define VMX_EXIT_REASON_RDRAND 0x00000039U 278 #define VMX_EXIT_REASON_INVPCID 0x0000003AU 279 #define VMX_EXIT_REASON_VMFUNC 0x0000003BU 280 #define VMX_EXIT_REASON_ENCLS 0x0000003CU 281 #define VMX_EXIT_REASON_RDSEED 0x0000003DU 282 #define VMX_EXIT_REASON_PAGE_MODIFICATION_LOG_FULL 0x0000003EU 283 #define VMX_EXIT_REASON_XSAVES 0x0000003FU 284 #define VMX_EXIT_REASON_XRSTORS 0x00000040U 285 #define VMX_EXIT_REASON_LOADIWKEY 0x00000045U 286 287 /* VMX execution control bits (pin based) */ 288 #define VMX_PINBASED_CTLS_IRQ_EXIT (1U<<0U) 289 #define VMX_PINBASED_CTLS_NMI_EXIT (1U<<3U) 290 #define VMX_PINBASED_CTLS_VIRT_NMI (1U<<5U) 291 #define VMX_PINBASED_CTLS_ENABLE_PTMR (1U<<6U) 292 #define VMX_PINBASED_CTLS_POST_IRQ (1U<<7U) 293 294 /* VMX execution control bits (processor based) */ 295 #define VMX_PROCBASED_CTLS_IRQ_WIN (1U<<2U) 296 #define VMX_PROCBASED_CTLS_TSC_OFF (1U<<3U) 297 #define VMX_PROCBASED_CTLS_HLT (1U<<7U) 298 #define VMX_PROCBASED_CTLS_INVLPG (1U<<9U) 299 #define VMX_PROCBASED_CTLS_MWAIT (1U<<10U) 300 #define VMX_PROCBASED_CTLS_RDPMC (1U<<11U) 301 #define VMX_PROCBASED_CTLS_RDTSC (1U<<12U) 302 #define VMX_PROCBASED_CTLS_CR3_LOAD (1U<<15U) 303 #define VMX_PROCBASED_CTLS_CR3_STORE (1U<<16U) 304 #define VMX_PROCBASED_CTLS_TERTIARY (1U<<17U) 305 #define VMX_PROCBASED_CTLS_CR8_LOAD (1U<<19U) 306 #define VMX_PROCBASED_CTLS_CR8_STORE (1U<<20U) 307 #define VMX_PROCBASED_CTLS_TPR_SHADOW (1U<<21U) 308 #define VMX_PROCBASED_CTLS_NMI_WINEXIT (1U<<22U) 309 #define VMX_PROCBASED_CTLS_MOV_DR (1U<<23U) 310 #define VMX_PROCBASED_CTLS_UNCOND_IO (1U<<24U) 311 #define VMX_PROCBASED_CTLS_IO_BITMAP (1U<<25U) 312 #define VMX_PROCBASED_CTLS_MON_TRAP (1U<<27U) 313 #define VMX_PROCBASED_CTLS_MSR_BITMAP (1U<<28U) 314 #define VMX_PROCBASED_CTLS_MONITOR (1U<<29U) 315 #define VMX_PROCBASED_CTLS_PAUSE (1U<<30U) 316 #define VMX_PROCBASED_CTLS_SECONDARY (1U<<31U) 317 #define VMX_PROCBASED_CTLS2_VAPIC (1U<<0U) 318 #define VMX_PROCBASED_CTLS2_EPT (1U<<1U) 319 #define VMX_PROCBASED_CTLS2_DESC_TABLE (1U<<2U) 320 #define VMX_PROCBASED_CTLS2_RDTSCP (1U<<3U) 321 #define VMX_PROCBASED_CTLS2_VX2APIC (1U<<4U) 322 #define VMX_PROCBASED_CTLS2_VPID (1U<<5U) 323 #define VMX_PROCBASED_CTLS2_WBINVD (1U<<6U) 324 #define VMX_PROCBASED_CTLS2_UNRESTRICT (1U<<7U) 325 #define VMX_PROCBASED_CTLS2_VAPIC_REGS (1U<<8U) 326 #define VMX_PROCBASED_CTLS2_VIRQ (1U<<9U) 327 #define VMX_PROCBASED_CTLS2_PAUSE_LOOP (1U<<10U) 328 #define VMX_PROCBASED_CTLS2_RDRAND (1U<<11U) 329 #define VMX_PROCBASED_CTLS2_INVPCID (1U<<12U) 330 #define VMX_PROCBASED_CTLS2_VM_FUNCS (1U<<13U) 331 #define VMX_PROCBASED_CTLS2_VMCS_SHADW (1U<<14U) 332 #define VMX_PROCBASED_CTLS2_ENCLS_EXIT (1U<<15U) 333 #define VMX_PROCBASED_CTLS2_RDSEED (1U<<16U) 334 #define VMX_PROCBASED_CTLS2_PML (1U<<17U) 335 #define VMX_PROCBASED_CTLS2_EPT_VE (1U<<18U) 336 #define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1U<<20U) 337 #define VMX_PROCBASED_CTLS2_PT_USE_GPA (1U<<22U) 338 #define VMX_PROCBASED_CTLS2_TSC_SCALING (1U<<25U) 339 #define VMX_PROCBASED_CTLS2_UWAIT_PAUSE (1U<<26U) 340 #define VMX_PROCBASED_CTLS2_ENCLV_EXIT (1U<<28U) 341 #define VMX_PROCBASED_CTLS3_LOADIWKEY (1U<<0U) 342 343 /* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */ 344 #define VMX_EPT_EXECUTE_ONLY (1UL << 0U) 345 #define VMX_EPT_PAGE_WALK_4 (1UL << 6U) 346 #define VMX_EPT_PAGE_WALK_5 (1UL << 7U) 347 #define VMX_EPTP_UC (1UL << 8U) 348 #define VMX_EPTP_WB (1UL << 14U) 349 #define VMX_EPT_2MB_PAGE (1UL << 16U) 350 #define VMX_EPT_1GB_PAGE (1UL << 17U) 351 #define VMX_EPT_INVEPT (1UL << 20U) 352 #define VMX_EPT_AD (1UL << 21U) 353 #define VMX_EPT_INVEPT_SINGLE_CONTEXT (1UL << 25U) 354 #define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1UL << 26U) 355 356 #define VMX_VPID_TYPE_INDIVIDUAL_ADDR 0UL 357 #define VMX_VPID_TYPE_SINGLE_CONTEXT 1UL 358 #define VMX_VPID_TYPE_ALL_CONTEXT 2UL 359 #define VMX_VPID_TYPE_SINGLE_NON_GLOBAL 3UL 360 361 #define VMX_VPID_INVVPID (1UL << 32U) 362 #define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1UL << 40U) 363 #define VMX_VPID_INVVPID_SINGLE_CONTEXT (1UL << 41U) 364 #define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1UL << 42U) 365 #define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1UL << 43U) 366 367 #define VMX_EPT_MT_EPTE_SHIFT 3U 368 #define VMX_EPTP_PWL_MASK 0x38UL 369 #define VMX_EPTP_PWL_4 0x18UL 370 #define VMX_EPTP_PWL_5 0x20UL 371 #define VMX_EPTP_AD_ENABLE_BIT (1UL << 6U) 372 #define VMX_EPTP_MT_MASK 0x7UL 373 #define VMX_EPTP_MT_WB 0x6UL 374 #define VMX_EPTP_MT_UC 0x0UL 375 376 /* VMX exit control bits */ 377 #define VMX_EXIT_CTLS_SAVE_DBG (1U<<2U) 378 #define VMX_EXIT_CTLS_HOST_ADDR64 (1U<<9U) 379 #define VMX_EXIT_CTLS_LOAD_PERF (1U<<12U) 380 #define VMX_EXIT_CTLS_ACK_IRQ (1U<<15U) 381 #define VMX_EXIT_CTLS_SAVE_PAT (1U<<18U) 382 #define VMX_EXIT_CTLS_LOAD_PAT (1U<<19U) 383 #define VMX_EXIT_CTLS_SAVE_EFER (1U<<20U) 384 #define VMX_EXIT_CTLS_LOAD_EFER (1U<<21U) 385 #define VMX_EXIT_CTLS_SAVE_PTMR (1U<<22U) 386 387 /* VMX entry control bits */ 388 #define VMX_ENTRY_CTLS_LOAD_DBG (1U<<2U) 389 #define VMX_ENTRY_CTLS_IA32E_MODE (1U<<9U) 390 #define VMX_ENTRY_CTLS_ENTRY_SMM (1U<<10U) 391 #define VMX_ENTRY_CTLS_DEACT_DUAL (1U<<11U) 392 #define VMX_ENTRY_CTLS_LOAD_PERF (1U<<13U) 393 #define VMX_ENTRY_CTLS_LOAD_PAT (1U<<14U) 394 #define VMX_ENTRY_CTLS_LOAD_EFER (1U<<15U) 395 396 /* VMX entry/exit Interrupt info */ 397 #define VMX_INT_INFO_ERR_CODE_VALID (1U<<11U) 398 #define VMX_INT_INFO_VALID (1U<<31U) 399 #define VMX_INT_TYPE_MASK (0x700U) 400 #define VMX_INT_TYPE_EXT_INT 0U 401 #define VMX_INT_TYPE_NMI 2U 402 #define VMX_INT_TYPE_HW_EXP 3U 403 #define VMX_INT_TYPE_SW_EXP 6U 404 405 /* Posted Interrupt Descriptor (PID) in VT-d spec */ 406 struct pi_desc { 407 /* Posted Interrupt Requests, one bit per requested vector */ 408 uint64_t pir[4]; 409 410 union { 411 struct { 412 /* Outstanding Notification */ 413 uint16_t on:1; 414 415 /* Suppress Notification, of non-urgent interrupts */ 416 uint16_t sn:1; 417 418 uint16_t rsvd_1:14; 419 420 /* Notification Vector */ 421 uint8_t nv; 422 423 uint8_t rsvd_2; 424 425 /* Notification destination, a physical LAPIC ID */ 426 uint32_t ndst; 427 } bits; 428 429 uint64_t value; 430 } control; 431 432 uint32_t rsvd[6]; 433 } __aligned(64); 434 435 436 /* External Interfaces */ 437 void vmx_on(void); 438 void vmx_off(void); 439 440 /** 441 * Read field from VMCS. 442 * 443 * Refer to Chapter 24, Vol. 3 in SDM for the width of VMCS fields. 444 * 445 * @return full contents in IA-32e mode for 64-bit fields. 446 * @return the lower 32-bit outside IA-32e mode for 64-bit fields. 447 * @return full contents for 32-bit fields, with higher 32-bit set to 0. 448 */ 449 uint16_t exec_vmread16(uint32_t field); 450 uint32_t exec_vmread32(uint32_t field); 451 uint64_t exec_vmread64(uint32_t field_full); 452 #define exec_vmread exec_vmread64 453 454 void exec_vmwrite16(uint32_t field, uint16_t value); 455 void exec_vmwrite32(uint32_t field, uint32_t value); 456 void exec_vmwrite64(uint32_t field_full, uint64_t value); 457 #define exec_vmwrite exec_vmwrite64 458 459 void exec_vmclear(void *addr); 460 void exec_vmptrld(void *addr); 461 void clear_va_vmcs(const uint8_t *vmcs_va); 462 void load_va_vmcs(const uint8_t *vmcs_va); 463 464 void init_cr0_cr4_flexible_bits(void); 465 bool is_valid_cr0_cr4(uint64_t cr0, uint64_t cr4); 466 467 #define POSTED_INTR_ON 0U 468 #endif /* VMX_H_ */ 469