1 /* 2 * Copyright (C) 2020-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RDT_H 8 #define RDT_H 9 10 enum { 11 RDT_RESOURCE_L3, 12 RDT_RESOURCE_L2, 13 RDT_RESOURCE_MBA, 14 15 /* Must be the last */ 16 RDT_NUM_RESOURCES, 17 }; 18 19 #define RDT_RESID_L3 1U 20 #define RDT_RESID_L2 2U 21 #define RDT_RESID_MBA 3U 22 23 extern const uint16_t hv_clos; 24 25 /* The instance of one RES_ID */ 26 struct rdt_ins { 27 union { 28 struct { 29 uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way 30 may be used by other entities in the platform (e.g. GPU) */ 31 uint16_t cbm_len; /* Length of Cache mask in bits */ 32 bool is_cdp_enabled; /* True if support CDP */ 33 } cache; 34 struct rdt_membw { 35 uint16_t mba_max; /* Max MBA delay throttling value supported */ 36 bool delay_linear; /* True if memory B/W delay is in linear scale */ 37 } membw; 38 } res; 39 uint16_t num_closids; /* Number of CLOSIDs available, 0 indicates resource is not supported.*/ 40 41 uint32_t num_clos_config; /* Number of element in clos_config_array */ 42 union clos_config *clos_config_array; 43 uint64_t cpu_mask; /* the CPUs this RDT applies */ 44 }; 45 46 /* The intel Resource Director Tech(RDT) based Allocation Tech support */ 47 struct rdt_type { 48 uint32_t res_id; /* RDT_RESID_L3/RDT_RESID_L2/RDT_RESID_MBA */ 49 uint32_t msr_qos_cfg; /* MSR addr to IA32_L3/L2_QOS_CFG */ 50 uint32_t msr_base; /* MSR base to program clos value */ 51 52 uint32_t num_ins; /* Number of element in ins_array */ 53 struct rdt_ins *ins_array; 54 }; 55 56 void setup_clos(uint16_t pcpu_id); 57 uint64_t clos2pqr_msr(uint16_t clos); 58 bool is_platform_rdt_capable(void); 59 const struct rdt_ins *get_rdt_res_ins(int res, uint16_t pcpu_id); 60 61 #endif /* RDT_H */ 62