1 /*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * Copyright (c) 2018-2022 Intel Corporation.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #ifndef VPCI_H_
30 #define VPCI_H_
31
32 #include <asm/lib/spinlock.h>
33 #include <lib/util.h>
34 #include <pci.h>
35 #include <list.h>
36
37 #define VDEV_LIST_HASHBITS 4U
38 #define VDEV_LIST_HASHSIZE (1U << VDEV_LIST_HASHBITS)
39
40 struct pci_vbar {
41 bool is_mem64hi; /* this is to indicate the high part of 64 bits MMIO bar */
42 bool sizing; /* this is to indicate the guest is sizing this BAR */
43 uint64_t size; /* BAR size */
44 uint64_t base_gpa; /* BAR guest physical address */
45 uint64_t base_hpa; /* BAR host physical address */
46 union pci_bar_type bar_type; /* the low 2(PIO)/4(MMIO) bits of BAR */
47 uint32_t mask; /* BAR size mask */
48 };
49
50 struct msix_table_entry {
51 uint64_t addr;
52 uint32_t data;
53 uint32_t vector_control;
54 };
55
56 /* MSI capability structure */
57 struct pci_msi {
58 bool is_64bit;
59 uint32_t capoff;
60 uint32_t caplen;
61 };
62
63 /* MSI-X capability structure */
64 struct msixcap {
65 uint8_t capid;
66 uint8_t nextptr;
67 uint16_t msgctrl;
68 uint32_t table_info; /* bar index and offset */
69 uint32_t pba_info; /* bar index and offset */
70 } __packed;
71
72 struct pci_msix {
73 struct msix_table_entry table_entries[CONFIG_MAX_MSIX_TABLE_NUM];
74 uint64_t mmio_gpa;
75 uint64_t mmio_hpa;
76 uint64_t mmio_size;
77 uint32_t capoff;
78 uint32_t caplen;
79 uint32_t table_bar;
80 uint32_t table_offset;
81 uint32_t table_count;
82 bool is_vmsix_on_msi;
83 bool is_vmsix_on_msi_programmed;
84 };
85
86 /* SRIOV capability structure */
87 struct pci_cap_sriov {
88 uint32_t capoff;
89 uint32_t caplen;
90
91 /*
92 * If the vdev is a SRIOV PF vdev, the vbars is used to store
93 * the bar information that is using to initialize SRIOV VF vdev bar.
94 */
95 struct pci_vbar vbars[PCI_BAR_COUNT];
96 };
97
98 union pci_cfgdata {
99 uint8_t data_8[PCIE_CONFIG_SPACE_SIZE];
100 uint16_t data_16[PCIE_CONFIG_SPACE_SIZE >> 1U];
101 uint32_t data_32[PCIE_CONFIG_SPACE_SIZE >> 2U];
102 };
103
104 struct pci_vdev;
105 struct pci_vdev_ops {
106 void (*init_vdev)(struct pci_vdev *vdev);
107 void (*deinit_vdev)(struct pci_vdev *vdev);
108 int32_t (*write_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
109 int32_t (*read_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
110 };
111
112 struct pci_vdev {
113 uint32_t id;
114 struct acrn_vpci *vpci;
115 /* The bus/device/function triple of the virtual PCI device. */
116 union pci_bdf bdf;
117
118 struct pci_pdev *pdev;
119
120 union pci_cfgdata cfgdata;
121
122 uint32_t flags;
123
124 /* The bar info of the virtual PCI device. */
125 uint32_t nr_bars; /* 6 for normal device, 2 for bridge, 1 for cardbus */
126 struct pci_vbar vbars[PCI_BAR_COUNT];
127
128 uint8_t prev_capoff; /* Offset of previous vPCI capability */
129 uint8_t free_capoff; /* Next free offset to add vPCI capability */
130
131 struct pci_msi msi;
132 struct pci_msix msix;
133 struct pci_cap_sriov sriov;
134
135 /* Pointer to the SRIOV VF associated PF's vdev */
136 struct pci_vdev *phyfun;
137
138 /* Pointer to corresponding PCI device's vm_config */
139 struct acrn_vm_pci_dev_config *pci_dev_config;
140
141 /* Pointer to corressponding operations */
142 const struct pci_vdev_ops *vdev_ops;
143
144 /*
145 * vdev in | HV | pre-VM | Service VM | post-VM
146 * | | |vdev used by Service VM|vdev used by post-VM|
147 * ----------------------------------------------------------------------------------------------------------
148 * parent_user| NULL(HV) | NULL(HV) | NULL(HV) | NULL(HV) | vdev in Service VM
149 * ----------------------------------------------------------------------------------------------------------
150 * user | vdev in HV | vdev in pre-VM | vdev in Service VM | vdev in post-VM | vdev in post-VM
151 */
152 struct pci_vdev *parent_user;
153 struct pci_vdev *user; /* NULL means this device is not used or is a zombie VF */
154 struct hlist_node link;
155 void *priv_data;
156 };
157
158 union pci_cfg_addr_reg {
159 uint32_t value;
160 struct {
161 uint32_t reg_num : 8; /* BITs 0-7, Register Number (BITs 0-1, always reserve to 0) */
162 uint32_t bdf : 16; /* BITs 8-23, BDF Number */
163 uint32_t resv : 7; /* BITs 24-30, Reserved */
164 uint32_t enable : 1; /* BITs 31, Enable bit */
165 } bits;
166 };
167
168 /* start address & end address of MMIO BAR */
169 struct pci_mmio_res {
170 uint64_t start;
171 uint64_t end;
172 };
173
174 struct acrn_vpci {
175 spinlock_t lock;
176 union pci_cfg_addr_reg addr;
177 struct pci_mmcfg_region pci_mmcfg;
178 struct pci_mmio_res res32; /* 32-bit mmio start/end address */
179 struct pci_mmio_res res64; /* 64-bit mmio start/end address */
180 struct pci_vdev pci_vdevs[CONFIG_MAX_PCI_DEV_NUM];
181 uint64_t vdev_bitmaps[INT_DIV_ROUNDUP(CONFIG_MAX_PCI_DEV_NUM, 64U)];
182 struct hlist_head vdevs_hlist_heads [VDEV_LIST_HASHSIZE];
183 };
184
185 struct acrn_vm;
186
187 extern const struct pci_vdev_ops vhostbridge_ops;
188 extern const struct pci_vdev_ops vpci_bridge_ops;
189 extern const struct pci_vdev_ops vpci_mf_dev_ops;
190 int32_t init_vpci(struct acrn_vm *vm);
191 void deinit_vpci(struct acrn_vm *vm);
192 struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf);
193 struct acrn_pcidev;
194 int32_t vpci_assign_pcidev(struct acrn_vm *tgt_vm, struct acrn_pcidev *pcidev);
195 int32_t vpci_deassign_pcidev(struct acrn_vm *tgt_vm, struct acrn_pcidev *pcidev);
196 struct pci_vdev *vpci_init_vdev(struct acrn_vpci *vpci, struct acrn_vm_pci_dev_config *dev_config, struct pci_vdev *parent_pf_vdev);
197 void vpci_deinit_vdev(struct pci_vdev *vdev);
198
is_pci_io_bar(struct pci_vbar * vbar)199 static inline bool is_pci_io_bar(struct pci_vbar *vbar)
200 {
201 return ((vbar->bar_type.io_space.indicator == 1U) && (!vbar->is_mem64hi));
202 }
203
is_pci_mem_bar(struct pci_vbar * vbar)204 static inline bool is_pci_mem_bar(struct pci_vbar *vbar)
205 {
206 return ((vbar->is_mem64hi) || ((vbar->bar_type.mem_space.indicator == 0U)));
207 }
208
209 /* Reserved PCI BAR type: 1.Memory bar with reserved memory type; 2.IO bar reserved bit is set */
is_pci_reserved_bar(struct pci_vbar * vbar)210 static inline bool is_pci_reserved_bar(struct pci_vbar *vbar)
211 {
212 return (((vbar->bar_type.mem_space.indicator == 0U) && ((vbar->bar_type.mem_space.mem_type & 0x1U) == 0x1U) && (!vbar->is_mem64hi)) ||
213 ((vbar->bar_type.io_space.indicator == 1U) && (vbar->bar_type.io_space.reserved == 1U)));
214 }
215
is_pci_mem32_bar(struct pci_vbar * vbar)216 static inline bool is_pci_mem32_bar(struct pci_vbar *vbar)
217 {
218 return ((vbar->bar_type.mem_space.indicator == 0U) && (vbar->bar_type.mem_space.mem_type == 0U) && (!vbar->is_mem64hi));
219 }
220
is_pci_mem64lo_bar(struct pci_vbar * vbar)221 static inline bool is_pci_mem64lo_bar(struct pci_vbar *vbar)
222 {
223 return ((vbar->bar_type.mem_space.indicator == 0U) && (vbar->bar_type.mem_space.mem_type == 2U) && (!vbar->is_mem64hi));
224 }
225 #endif /* VPCI_H_ */
226