1 /*
2 * Copyright (C) 2018-2022 Intel Corporation.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /*
8 * cpuid.h
9 *
10 * Created on: Jan 4, 2018
11 * Author: don
12 */
13
14 #ifndef CPUID_H_
15 #define CPUID_H_
16
17 /* CPUID bit definitions */
18 #define CPUID_ECX_SSE3 (1U<<0U)
19 #define CPUID_ECX_PCLMUL (1U<<1U)
20 #define CPUID_ECX_DTES64 (1U<<2U)
21 #define CPUID_ECX_MONITOR (1U<<3U)
22 #define CPUID_ECX_DS_CPL (1U<<4U)
23 #define CPUID_ECX_VMX (1U<<5U)
24 #define CPUID_ECX_SMX (1U<<6U)
25 #define CPUID_ECX_EST (1U<<7U)
26 #define CPUID_ECX_TM2 (1U<<8U)
27 #define CPUID_ECX_SSSE3 (1U<<9U)
28 #define CPUID_ECX_CID (1U<<10U)
29 #define CPUID_ECX_SDBG (1U<<11U)
30 #define CPUID_ECX_FMA (1U<<12U)
31 #define CPUID_ECX_CX16 (1U<<13U)
32 #define CPUID_ECX_ETPRD (1U<<14U)
33 #define CPUID_ECX_PDCM (1U<<15U)
34 #define CPUID_ECX_DCA (1U<<18U)
35 #define CPUID_ECX_SSE4_1 (1U<<19U)
36 #define CPUID_ECX_SSE4_2 (1U<<20U)
37 #define CPUID_ECX_x2APIC (1U<<21U)
38 #define CPUID_ECX_MOVBE (1U<<22U)
39 #define CPUID_ECX_POPCNT (1U<<23U)
40 #define CPUID_ECX_AES (1U<<25U)
41 #define CPUID_ECX_XSAVE (1U<<26U)
42 #define CPUID_ECX_OSXSAVE (1U<<27U)
43 #define CPUID_ECX_AVX (1U<<28U)
44 #define CPUID_ECX_HV (1U<<31U)
45 #define CPUID_ECX_MWAIT (1U<<0U)
46 #define CPUID_ECX_MWAIT_INT (1U<<1U)
47 #define CPUID_EDX_FPU (1U<<0U)
48 #define CPUID_EDX_VME (1U<<1U)
49 #define CPUID_EDX_DE (1U<<2U)
50 #define CPUID_EDX_PSE (1U<<3U)
51 #define CPUID_EDX_TSC (1U<<4U)
52 #define CPUID_EDX_MSR (1U<<5U)
53 #define CPUID_EDX_PAE (1U<<6U)
54 #define CPUID_EDX_MCE (1U<<7U)
55 #define CPUID_EDX_CX8 (1U<<8U)
56 #define CPUID_EDX_APIC (1U<<9U)
57 #define CPUID_EDX_SEP (1U<<11U)
58 #define CPUID_EDX_MTRR (1U<<12U)
59 #define CPUID_EDX_PGE (1U<<13U)
60 #define CPUID_EDX_MCA (1U<<14U)
61 #define CPUID_EDX_CMOV (1U<<15U)
62 #define CPUID_EDX_PAT (1U<<16U)
63 #define CPUID_EDX_PSE36 (1U<<17U)
64 #define CPUID_EDX_PSN (1U<<18U)
65 #define CPUID_EDX_CLF (1U<<19U)
66 #define CPUID_EDX_DTES (1U<<21U)
67 #define CPUID_EDX_ACPI (1U<<22U)
68 #define CPUID_EDX_MMX (1U<<23U)
69 #define CPUID_EDX_FXSR (1U<<24U)
70 #define CPUID_EDX_SSE (1U<<25U)
71 #define CPUID_EDX_SSE2 (1U<<26U)
72 #define CPUID_EDX_SS (1U<<27U)
73 #define CPUID_EDX_HTT (1U<<28U)
74 #define CPUID_EDX_TM1 (1U<<29U)
75 #define CPUID_EDX_IA64 (1U<<30U)
76 #define CPUID_EDX_PBE (1U<<31U)
77 /* CPUID.06H:EAX.ECMD */
78 #define CPUID_EAX_ECMD (1U<<5U)
79 /* CPUID.06H:EAX.HWP */
80 #define CPUID_EAX_HWP (1U<<7U)
81 /* CPUID.06H:EAX.HWP_Notification */
82 #define CPUID_EAX_HWP_N (1U<<8U)
83 /* CPUID.06H:EAX.HWP_Activity_Window */
84 #define CPUID_EAX_HWP_AW (1U<<9U)
85 /* CPUID.06H:EAX.HWP_Energy_Performance_Preference */
86 #define CPUID_EAX_HWP_EPP (1U<<10U)
87 /* CPUID.06H:EAX.HWP_Package_Level_Request */
88 #define CPUID_EAX_HWP_PLR (1U<<11U)
89 /* CPUID.06H:EAX.Hardware_Feedback_Interface */
90 #define CPUID_EAX_HFI (1U<<19U)
91 /* CPUID.06H:EAX.HWP_control */
92 #define CPUID_EAX_HWP_CTL (1U<<22U)
93 /* CPUID.06H:EAX.Intel_Thread_Director */
94 #define CPUID_EAX_ITD (1U<<23U)
95 /* CPUID.06H:ECX.Hardware_Coordination_Feedback_Capability */
96 #define CPUID_ECX_HCFC (1U<<0U)
97 /* CPUID.07H:EBX.FSGSBASE*/
98 #define CPUID_EBX_FSGSBASE (1U<<0U)
99 /* CPUID.07H:EBX.TSC_ADJUST*/
100 #define CPUID_EBX_TSC_ADJ (1U<<1U)
101 /* CPUID.07H:EBX.SGX */
102 #define CPUID_EBX_SGX (1U<<2U)
103 /* CPUID.07H:EBX.SMEP*/
104 #define CPUID_EBX_SMEP (1U<<7U)
105 /* CPUID.07H:EBX.MPX */
106 #define CPUID_EBX_MPX (1U<<14U)
107 /* CPUID.07H:EBX.SMAP*/
108 #define CPUID_EBX_SMAP (1U<<20U)
109 /* CPUID.07H:ECX.UMIP */
110 #define CPUID_ECX_UMIP (1U<<2U)
111 /* CPUID.07H:ECX.PKE */
112 #define CPUID_ECX_PKE (1U<<3U)
113 /* CPUID.07H:ECX.WAITPKG */
114 #define CPUID_ECX_WAITPKG (1U<<5U)
115 /* CPUID.07H:ECX.CET_SS */
116 #define CPUID_ECX_CET_SS (1U<<7U)
117 /* CPUID.07H:ECX.LA57 */
118 #define CPUID_ECX_LA57 (1U<<16U)
119 /* CPUID.07H:ECX.SGX_LC*/
120 #define CPUID_ECX_SGX_LC (1U<<30U)
121 /* CPUID.07H:ECX.PKS*/
122 #define CPUID_ECX_PKS (1U<<31U)
123 /* CPUID.07H:EDX.Hybrid */
124 #define CPUID_EDX_HYBRID (1U<<15U)
125 /* CPUID.07H:EDX.CET_IBT */
126 #define CPUID_EDX_CET_IBT (1U<<20U)
127 /* CPUID.07H:EDX.IBRS_IBPB*/
128 #define CPUID_EDX_IBRS_IBPB (1U<<26U)
129 /* CPUID.07H:EDX.STIBP*/
130 #define CPUID_EDX_STIBP (1U<<27U)
131 /* CPUID.80000001H:EDX.Page1GB*/
132 #define CPUID_EDX_PAGE1GB (1U<<26U)
133 /* CPUID.07H:EBX.INVPCID*/
134 #define CPUID_EBX_INVPCID (1U<<10U)
135 /* CPUID.07H:EBX.PQM */
136 #define CPUID_EBX_PQM (1U<<12U)
137 /* CPUID.07H:EBX.PQE */
138 #define CPUID_EBX_PQE (1U<<15U)
139 /* CPUID.07H:EBX.INTEL_PROCESSOR_TRACE */
140 #define CPUID_EBX_PROC_TRC (1U<<25U)
141 /* CPUID.01H:ECX.PCID*/
142 #define CPUID_ECX_PCID (1U<<17U)
143 /* CPUID.0DH.EAX.XCR0_BNDREGS */
144 #define CPUID_EAX_XCR0_BNDREGS (1U<<3U)
145 /* CPUID.0DH.EAX.XCR0_BNDCSR */
146 #define CPUID_EAX_XCR0_BNDCSR (1U<<4U)
147 /* CPUID.0DH.ECX.CET_U_STATE */
148 #define CPUID_ECX_CET_U_STATE (1U<<11U)
149 /* CPUID.0DH.ECX.CET_S_STATE */
150 #define CPUID_ECX_CET_S_STATE (1U<<12U)
151 /* CPUID.12H.EAX.SGX1 */
152 #define CPUID_EAX_SGX1 (1U<<0U)
153 /* CPUID.12H.EAX.SGX2 */
154 #define CPUID_EAX_SGX2 (1U<<1U)
155 /* CPUID.19H.EBX.KL_AES_ENABLED */
156 #define CPUID_EBX_KL_AES_EN (1U<<0U)
157 /* CPUID.19H.EBX.KL_BACKUP_MSR */
158 #define CPUID_EBX_KL_BACKUP_MSR (1U<<4U)
159 /* CPUID.19H.ECX.KL_NOBACKUP */
160 #define CPUID_ECX_KL_NOBACKUP (1U<<0U)
161 /* CPUID.19H.ECX.KL_RANDOM_KS */
162 #define CPUID_ECX_KL_RANDOM_KS (1U<<1U)
163 /* CPUID.80000001H.EDX.XD_BIT_AVAILABLE */
164 #define CPUID_EDX_XD_BIT_AVIL (1U<<20U)
165
166 /* CPUID source operands */
167 #define CPUID_VENDORSTRING 0U
168 #define CPUID_FEATURES 1U
169 #define CPUID_TLB 2U
170 #define CPUID_SERIALNUM 3U
171 #define CPUID_CACHE 4U
172 #define CPUID_THERMAL_POWER 6U
173 #define CPUID_EXTEND_FEATURE 7U
174 #define CPUID_ARCH_PERF_MON 0xAU
175 #define CPUID_EXTEND_TOPOLOGY 0xBU
176 #define CPUID_XSAVE_FEATURES 0xDU
177 #define CPUID_RDT_MONITOR 0xFU
178 #define CPUID_RDT_ALLOCATION 0x10U
179 #define CPUID_SGX_CAP 0x12U
180 #define CPUID_TRACE 0x14U
181 #define CPUID_FREQ 0x16U
182 #define CPUID_ADDR_TRANS 0x18U
183 #define CPUID_KEY_LOCKER 0x19U
184 #define CPUID_MODEL_ID 0x1AU
185 #define CPUID_PCONFIG 0x1BU
186 #define CPUID_LAST_BRANCH_RECORD 0x1CU
187 #define CPUID_V2_EXTEND_TOPOLOGY 0x1FU
188 #define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U
189 #define CPUID_EXTEND_FUNCTION_1 0x80000001U
190 #define CPUID_EXTEND_FUNCTION_2 0x80000002U
191 #define CPUID_EXTEND_FUNCTION_3 0x80000003U
192 #define CPUID_EXTEND_FUNCTION_4 0x80000004U
193 #define CPUID_EXTEND_CACHE 0x80000006U
194 #define CPUID_EXTEND_INVA_TSC 0x80000007U
195 #define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U
196
cpuid_subleaf(uint32_t leaf,uint32_t subleaf,uint32_t * eax,uint32_t * ebx,uint32_t * ecx,uint32_t * edx)197 static inline void cpuid_subleaf(uint32_t leaf, uint32_t subleaf,
198 uint32_t *eax, uint32_t *ebx,
199 uint32_t *ecx, uint32_t *edx)
200 {
201 /* Execute CPUID instruction and save results */
202 asm volatile("cpuid":"=a"(*eax), "=b"(*ebx),
203 "=c"(*ecx), "=d"(*edx)
204 : "a" (leaf), "c" (subleaf)
205 : "memory");
206 }
207
208 #endif /* CPUID_H_ */
209