1 /*
2 * Copyright (c) 2021-2022 Intel Corporation.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 */
7
8 #include <logmsg.h>
9 #include <pci.h>
10 #include <asm/guest/vm.h>
11 #include <acrn_common.h>
12 #include "vroot_port.h"
13
14 #include "vpci_priv.h"
15
16 #define PCIE_CAP_VPOS 0x40 /* pcie capability reg position */
17 #define PTM_CAP_VPOS PCI_ECAP_BASE_PTR /* ptm capability reg postion */
18
init_vrp(struct pci_vdev * vdev)19 static void init_vrp(struct pci_vdev *vdev)
20 {
21 /* vendor and device */
22 pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, VRP_VENDOR);
23 pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, VRP_DEVICE);
24
25 /* status register */
26 pci_vdev_write_vcfg(vdev, PCIR_STATUS, 2U, PCIM_STATUS_CAPPRESENT);
27
28 /* rev id */
29 pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0x01U);
30
31 /* sub class */
32 pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_PCI);
33
34 /* class */
35 pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE);
36
37 /* Header Type */
38 pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, PCIM_HDRTYPE_BRIDGE);
39
40 /* capability pointer */
41 pci_vdev_write_vcfg(vdev, PCIR_CAP_PTR, 1U, PCIE_CAP_VPOS);
42
43 /* pcie capability registers */
44 pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCICAP_ID, 1U, PCIY_PCIE);
45
46 /* bits (3:0): capability version = 010b
47 * bits (7:4) device/port type = 0100b (root port of pci-e)
48 * bits (8) -- slot implemented = 1b
49 */
50 pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCICAP_EXP_CAP, 2U, 0x0142);
51
52 /* It seems important that passthru device's max payload settings match
53 * the settings on the native device otherwise passthru device may not work.
54 * So we have to set vrp's max payload capacity as native root port
55 * otherwise we may accidentally change passthru device's max payload since
56 * during guest OS's pci device enumeration, pass-thru device will renegotiate
57 * its max payload's setting with vrp.
58 */
59 pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCIR_PCIE_DEVCAP, 4U,
60 vdev->pci_dev_config->vrp_max_payload);
61
62 /* In theory, we don't need to program dev ctr's max payload and hopefully OS
63 * will program it but we cannot always rely on OS to program
64 * this register.
65 */
66 pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCIR_PCIE_DEVCTRL, 2U,
67 (vdev->pci_dev_config->vrp_max_payload << 5) & PCIM_PCIE_DEV_CTRL_MAX_PAYLOAD);
68
69 vdev->parent_user = NULL;
70 vdev->user = vdev;
71 }
72
deinit_vrp(__unused struct pci_vdev * vdev)73 static void deinit_vrp(__unused struct pci_vdev *vdev)
74 {
75 vdev->parent_user = NULL;
76 vdev->user = NULL;
77 }
78
read_vrp_cfg(struct pci_vdev * vdev,uint32_t offset,uint32_t bytes,uint32_t * val)79 static int32_t read_vrp_cfg(struct pci_vdev *vdev, uint32_t offset,
80 uint32_t bytes, uint32_t *val)
81 {
82 *val = pci_vdev_read_vcfg(vdev, offset, bytes);
83
84 return 0;
85 }
86
write_vrp_cfg(__unused struct pci_vdev * vdev,__unused uint32_t offset,__unused uint32_t bytes,__unused uint32_t val)87 static int32_t write_vrp_cfg(__unused struct pci_vdev *vdev, __unused uint32_t offset,
88 __unused uint32_t bytes, __unused uint32_t val)
89 {
90 pci_vdev_write_vcfg(vdev, offset, bytes, val);
91
92 return 0;
93 }
94
95 /*
96 * @pre vdev != NULL
97 * @pre vrp_config != NULL
98 */
init_ptm(struct pci_vdev * vdev,struct vrp_config * vrp_config)99 static void init_ptm(struct pci_vdev *vdev, struct vrp_config *vrp_config)
100 {
101 /* ptm capability register */
102 if (vrp_config->ptm_capable)
103 {
104 pci_vdev_write_vcfg(vdev, PTM_CAP_VPOS, PCI_PTM_CAP_LEN, 0x0001001f);
105
106 pci_vdev_write_vcfg(vdev, PTM_CAP_VPOS + PCIR_PTM_CAP, PCI_PTM_CAP_LEN, 0x406);
107
108 pci_vdev_write_vcfg(vdev, PTM_CAP_VPOS + PCIR_PTM_CTRL, PCI_PTM_CAP_LEN, 0x3);
109 }
110
111 /* emulate bus numbers */
112 pci_vdev_write_vcfg(vdev, PCIR_PRIBUS_1, 1U, 0x00); /* virtual root port always connects to host bridge */
113 pci_vdev_write_vcfg(vdev, PCIR_SECBUS_1, 1U, vrp_config->secondary_bus);
114 pci_vdev_write_vcfg(vdev, PCIR_SUBBUS_1, 1U, vrp_config->subordinate_bus);
115 }
116
create_vrp(struct acrn_vm * vm,struct acrn_vdev * dev)117 int32_t create_vrp(struct acrn_vm *vm, struct acrn_vdev *dev)
118 {
119 int32_t ret = 0;
120 struct acrn_vm_config *vm_config = get_vm_config(vm->vm_id);
121 struct acrn_vm_pci_dev_config *dev_config = NULL;
122 struct pci_vdev *vdev;
123 struct vrp_config *vrp_config;
124
125 uint16_t i;
126
127 vrp_config = (struct vrp_config*)dev->args;
128
129 pr_acrnlog("%s: virtual root port phy_bdf=0x%x, vbdf=0x%x, vendor_id=0x%x, dev_id=0x%x,\
130 primary_bus=0x%x, secondary_bus=0x%x, sub_bus=0x%x.\n",
131 __func__, vrp_config->phy_bdf, dev->slot,
132 dev->id.fields.vendor, dev->id.fields.device,
133 vrp_config->primary_bus, vrp_config->secondary_bus, vrp_config->subordinate_bus);
134
135 for (i = 0U; i < vm_config->pci_dev_num; i++) {
136 dev_config = &vm_config->pci_devs[i];
137 if (dev_config->vrp_sec_bus == vrp_config->secondary_bus) {
138 dev_config->vbdf.value = (uint16_t)dev->slot;
139 dev_config->pbdf.value = vrp_config->phy_bdf;
140 dev_config->vrp_max_payload = vrp_config->max_payload;
141 dev_config->vdev_ops = &vrp_ops;
142
143 spinlock_obtain(&vm->vpci.lock);
144 vdev = vpci_init_vdev(&vm->vpci, dev_config, NULL);
145 spinlock_release(&vm->vpci.lock);
146 if (vdev == NULL) {
147 pr_err("%s: failed to create virtual root port\n", __func__);
148 ret = -EFAULT;
149 break;
150 }
151
152 init_ptm(vdev, vrp_config);
153
154 break;
155 }
156 }
157
158 return ret;
159 }
160
destroy_vrp(struct pci_vdev * vdev)161 int32_t destroy_vrp(struct pci_vdev *vdev)
162 {
163 struct acrn_vpci *vpci = vdev->vpci;
164
165 spinlock_obtain(&vpci->lock);
166 vpci_deinit_vdev(vdev);
167 spinlock_release(&vpci->lock);
168
169 return 0;
170 }
171
172 const struct pci_vdev_ops vrp_ops = {
173 .init_vdev = init_vrp,
174 .deinit_vdev = deinit_vrp,
175 .write_vdev_cfg = write_vrp_cfg,
176 .read_vdev_cfg = read_vrp_cfg,
177 };
178