1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CPUINFO_H 8 #define CPUINFO_H 9 10 #define MAX_PSTATE 20U /* max num of supported Px count */ 11 #define MAX_CSTATE 8U /* max num of supported Cx count */ 12 /* We support MAX_CSTATE num of Cx, means have (MAX_CSTATE - 1) Cx entries, 13 * i.e. supported Cx entry index range from 1 to MAX_CX_ENTRY. 14 */ 15 #define MAX_CX_ENTRY (MAX_CSTATE - 1U) 16 17 /* CPUID feature words */ 18 #define FEAT_1_ECX 0U /* CPUID[1].ECX */ 19 #define FEAT_1_EDX 1U /* CPUID[1].EDX */ 20 #define FEAT_7_0_EBX 2U /* CPUID[EAX=7,ECX=0].EBX */ 21 #define FEAT_7_0_ECX 3U /* CPUID[EAX=7,ECX=0].ECX */ 22 #define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */ 23 #define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */ 24 #define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */ 25 #define FEAT_8000_0007_EDX 7U /* CPUID[8000_0007].EDX */ 26 #define FEAT_8000_0008_EBX 8U /* CPUID[8000_0008].EBX */ 27 #define FEAT_D_0_EAX 9U /* CPUID[D][0].EAX */ 28 #define FEAT_D_0_EDX 10U /* CPUID[D][0].EDX */ 29 #define FEAT_D_1_EAX 11U /* CPUID[D][1].EAX */ 30 #define FEAT_D_1_ECX 13U /* CPUID[D][1].ECX */ 31 #define FEAT_D_1_EDX 14U /* CPUID[D][1].EDX */ 32 #define FEAT_7_2_EDX 15U /* CPUID[EAX=7,ECX=2].EDX */ 33 #define FEATURE_WORDS 16U 34 35 struct cpuinfo_x86 { 36 /* SDM 2-2 Vol.4 Table 2-1 uses DisplayFamily_DisplayModel to 37 * distinguish Processor Families/Processor Number Series. 38 */ 39 uint8_t displayfamily, displaymodel; 40 uint8_t virt_bits; 41 uint8_t phys_bits; 42 uint32_t cpuid_level; 43 uint32_t extended_cpuid_level; 44 uint64_t physical_address_mask; 45 uint32_t cpuid_leaves[FEATURE_WORDS]; 46 char model_name[64]; 47 }; 48 49 bool has_monitor_cap(void); 50 bool disable_host_monitor_wait(void); 51 bool is_apl_platform(void); 52 bool is_apicv_advanced_feature_supported(void); 53 bool pcpu_has_cap(uint32_t bit); 54 bool pcpu_has_vmx_ept_vpid_cap(uint64_t bit_mask); 55 bool is_apl_platform(void); 56 bool has_core_cap(uint32_t bit_mask); 57 bool is_ac_enabled(void); 58 bool is_gp_enabled(void); 59 void init_pcpu_capabilities(void); 60 void init_pcpu_model_name(void); 61 int32_t detect_hardware_support(void); 62 struct cpuinfo_x86 *get_pcpu_info(void); 63 64 /* The bits of MSR IA32_CORE_CAPABILITIES */ 65 #define CORE_CAP_SPLIT_LOCK (1U << 5U) /* support #AC for Split-locked Access */ 66 #define CORE_CAP_UC_LOCK (1U << 4U) /* support #GP for non-guaranteed-atomic-locked access at Non-WB memory */ 67 68 69 #endif /* CPUINFO_H */ 70