1 /*- 2 * Copyright (c) 2012 NetApp, Inc. 3 * Copyright (c) 2017-2022 Intel Corporation. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef INSTR_EMUL_H 30 #define INSTR_EMUL_H 31 32 #include <types.h> 33 #include <asm/cpu.h> 34 #include <asm/guest/guest_memory.h> 35 36 struct acrn_vcpu; 37 struct instr_emul_vie_op { 38 uint8_t op_type; /* type of operation (e.g. MOV) */ 39 uint16_t op_flags; 40 }; 41 42 #define VIE_PREFIX_SIZE 4U 43 #define VIE_INST_SIZE 15U 44 struct instr_emul_vie { 45 uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */ 46 uint8_t num_valid; /* size of the instruction */ 47 uint8_t num_processed; 48 49 struct acrn_vcpu *vcpu; 50 uint64_t rip; 51 52 uint8_t addrsize:4, opsize:4; /* address and operand sizes */ 53 uint8_t rex_w:1, /* REX prefix */ 54 rex_r:1, 55 rex_x:1, 56 rex_b:1, 57 rex_present:1, 58 repz_present:1, /* REP/REPE/REPZ prefix */ 59 repnz_present:1, /* REPNE/REPNZ prefix */ 60 opsize_override:1, /* Operand size override */ 61 addrsize_override:1, /* Address size override */ 62 seg_override:1; /* Segment override */ 63 64 uint8_t mod:2, /* ModRM byte */ 65 reg:4, 66 rm:4; 67 68 uint8_t ss:2, /* SIB byte */ 69 index:4, 70 base:4; 71 72 uint8_t disp_bytes; 73 uint8_t imm_bytes; 74 75 uint8_t scale; 76 enum cpu_reg_name base_register; /* CPU_REG_xyz */ 77 enum cpu_reg_name index_register; /* CPU_REG_xyz */ 78 enum cpu_reg_name segment_register; /* CPU_REG_xyz */ 79 80 int64_t displacement; /* optional addr displacement */ 81 int64_t immediate; /* optional immediate operand */ 82 83 uint8_t decoded; /* set to 1 if successfully decoded */ 84 85 uint8_t opcode; 86 struct instr_emul_vie_op op; /* opcode description */ 87 88 uint64_t dst_gpa; /* saved dst operand gpa. Only for movs */ 89 uint64_t gva; /* saved gva for instruction emulation */ 90 }; 91 92 struct instr_emul_ctxt { 93 struct instr_emul_vie vie; 94 }; 95 96 int32_t emulate_instruction(struct acrn_vcpu *vcpu); 97 int32_t decode_instruction(struct acrn_vcpu *vcpu, bool full_decode); 98 bool is_current_opcode_xchg(struct acrn_vcpu *vcpu); 99 100 #endif 101