1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VMCS_H_ 8 #define VMCS_H_ 9 10 #define VM_SUCCESS 0 11 #define VM_FAIL (-1) 12 13 #ifndef ASSEMBLER 14 #include <types.h> 15 #include <asm/guest/vcpu.h> 16 17 #define VMX_VMENTRY_FAIL 0x80000000U 18 19 #define APIC_ACCESS_OFFSET 0xFFFUL /* 11:0, offset within the APIC page */ 20 #define APIC_ACCESS_TYPE 0xF000UL /* 15:12, access type */ 21 #define TYPE_LINEAR_APIC_INST_READ (0UL << 12U) 22 #define TYPE_LINEAR_APIC_INST_WRITE (1UL << 12U) 23 24 /* VM exit qulifications for APIC-access 25 * Access type: 26 * 0 = linear access for a data read during instruction execution 27 * 1 = linear access for a data write during instruction execution 28 * 2 = linear access for an instruction fetch 29 * 3 = linear access (read or write) during event delivery 30 * 10 = guest-physical access during event delivery 31 * 15 = guest-physical access for an instructon fetch or during 32 * instruction execution 33 */ apic_access_type(uint64_t qual)34static inline uint64_t apic_access_type(uint64_t qual) 35 { 36 return (qual & APIC_ACCESS_TYPE); 37 } 38 apic_access_offset(uint64_t qual)39static inline uint64_t apic_access_offset(uint64_t qual) 40 { 41 return (qual & APIC_ACCESS_OFFSET); 42 } 43 clear_vmcs_bit(uint32_t vmcs_field,uint64_t bit)44static inline void clear_vmcs_bit(uint32_t vmcs_field, uint64_t bit) 45 { 46 uint64_t val64; 47 48 val64 = exec_vmread(vmcs_field); 49 val64 &= ~bit; 50 exec_vmwrite(vmcs_field, val64); 51 } 52 set_vmcs_bit(uint32_t vmcs_field,uint64_t bit)53static inline void set_vmcs_bit(uint32_t vmcs_field, uint64_t bit) 54 { 55 uint64_t val64; 56 57 val64 = exec_vmread(vmcs_field); 58 val64 |= bit; 59 exec_vmwrite(vmcs_field, val64); 60 } 61 62 void init_vmcs(struct acrn_vcpu *vcpu); 63 void load_vmcs(const struct acrn_vcpu *vcpu); 64 void init_host_state(void); 65 66 void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu); 67 #endif /* ASSEMBLER */ 68 69 #endif /* VMCS_H_ */ 70