1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * SPDX-License-Identifier: BSD-3-Clause 4 */ 5 6 #ifndef HOST_PM_H 7 #define HOST_PM_H 8 9 #include <acrn_common.h> 10 11 #define BIT_SLP_TYPx 10U 12 #define BIT_SLP_EN 13U 13 #define BIT_WAK_STS 15U 14 15 #define CF9_RESET_WARM 0x6 16 #define CF9_RESET_COLD 0xE 17 18 struct cpu_state_info { 19 uint8_t px_cnt; /* count of all Px states */ 20 const struct acrn_pstate_data *px_data; 21 uint8_t cx_cnt; /* count of all Cx entries */ 22 const struct acrn_cstate_data *cx_data; 23 }; 24 25 struct cpu_state_table { 26 char model_name[64]; 27 struct cpu_state_info state_info; 28 }; 29 30 struct acpi_reset_reg { 31 struct acrn_acpi_generic_address reg; 32 uint8_t val; 33 }; 34 35 struct pm_s_state_data *get_host_sstate_data(void); 36 void host_enter_s3(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val); 37 void shutdown_system(void); 38 void save_s5_reg_val(uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val); 39 void do_acpi_sx(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val); 40 extern void asm_enter_s3(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val); 41 extern void restore_s3_context(void); 42 struct cpu_state_info *get_cpu_pm_state_info(void); 43 struct acpi_reset_reg *get_host_reset_reg_data(void); 44 void reset_host(bool warm); 45 void init_frequency_policy(void); 46 void apply_frequency_policy(void); 47 48 #endif /* HOST_PM_H */ 49