1 /* 2 * Copyright (C) 2018 Intel Corporation. 3 * SPDX-License-Identifier: BSD-3-Clause 4 */ 5 6 #ifndef _NPK_H_ 7 #define _NPK_H_ 8 9 #define NPK_DRV_SYSFS_PATH "/sys/bus/pci/drivers/intel_th_pci" 10 11 #define NPK_CSR_MTB_BAR_SZ 0x100000 12 13 #define NPK_CSR_GTH_BASE 0 14 #define NPK_CSR_GTH_SZ 0xF0 15 #define NPK_CSR_GTHOPT0 0x0 16 #define NPK_CSR_SWDEST_0 0x8 17 #define NPK_CSR_GSWDEST 0x88 18 #define NPK_CSR_GTHSTAT 0xD4 19 #define NPK_CSR_GTHSTAT_PLE 0xFF 20 21 #define NPK_CSR_STH_BASE 0x4000 22 #define NPK_CSR_STH_SZ 0x80 23 #define NPK_CSR_STHCAP0 0x0 24 #define NPK_CSR_STHCAP1 0x4 25 26 #define NPK_CSR_MSC0_BASE 0xA0100 27 #define NPK_CSR_MSC0_SZ 0x20 28 #define NPK_CSR_MSCxCTL 0x0 29 #define NPK_CSR_MSCxSTS 0x4 30 #define NPK_CSR_MSCxSTS_PLE 0x4 31 32 #define NPK_CSR_MSC1_BASE 0xA0200 33 #define NPK_CSR_MSC1_SZ 0x20 34 35 #define NPK_CSR_PTI_BASE 0x1C00 36 #define NPK_CSR_PTI_SZ 0x4 37 38 #define NPK_SW_MSTR_STRT 256 39 #define NPK_SW_MSTR_STP 1024 40 #define NPK_SW_MSTR_NUM (NPK_SW_MSTR_STP - NPK_SW_MSTR_STRT) 41 #define NPK_CHANNELS_PER_MSTR 128 42 #define NPK_MSTR_TO_MEM_SZ(x) ((x) * NPK_CHANNELS_PER_MSTR * 64) 43 44 enum npk_regs_name { 45 NPK_CSR_FIRST, 46 NPK_CSR_GTH = NPK_CSR_FIRST, 47 NPK_CSR_STH, 48 NPK_CSR_MSC0, 49 NPK_CSR_MSC1, 50 NPK_CSR_PTI, 51 NPK_CSR_LAST, 52 }; 53 54 struct npk_regs { 55 uint32_t base; 56 uint32_t size; 57 union { 58 uint8_t *u8; 59 uint32_t *u32; 60 } data; 61 } __packed; 62 63 struct npk_reg_default_val { 64 enum npk_regs_name csr; 65 int offset; 66 uint32_t default_val; 67 }; 68 69 #endif /* _NPK_H_ */ 70