1 /* 2 * Copyright (C) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 5 * 6 * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 7 * All rights reserved. 8 */ 9 10 #ifndef _VGA_H_ 11 #define _VGA_H_ 12 13 #include "gc.h" 14 #include "vdisplay.h" 15 16 #define VGA_IOPORT_START 0x3c0 17 #define VGA_IOPORT_END 0x3df 18 19 /* General registers */ 20 #define GEN_INPUT_STS0_PORT 0x3c2 21 #define GEN_FEATURE_CTRL_PORT 0x3ca 22 #define GEN_MISC_OUTPUT_PORT 0x3cc 23 #define GEN_INPUT_STS1_MONO_PORT 0x3ba 24 #define GEN_INPUT_STS1_COLOR_PORT 0x3da 25 #define GEN_IS1_VR 0x08 /* Vertical retrace */ 26 #define GEN_IS1_DE 0x01 /* Display enable not */ 27 28 /* Attribute controller registers. */ 29 #define ATC_IDX_PORT 0x3c0 30 #define ATC_DATA_PORT 0x3c1 31 32 #define ATC_IDX_MASK 0x1f 33 #define ATC_PALETTE0 0 34 #define ATC_PALETTE15 15 35 #define ATC_MODE_CONTROL 16 36 #define ATC_MC_IPS 0x80 /* Internal palette size */ 37 #define ATC_MC_GA 0x01 /* Graphics/alphanumeric */ 38 #define ATC_OVERSCAN_COLOR 17 39 #define ATC_COLOR_PLANE_ENABLE 18 40 #define ATC_HORIZ_PIXEL_PANNING 19 41 #define ATC_COLOR_SELECT 20 42 #define ATC_CS_C67 0x0c /* Color select bits 6+7 */ 43 #define ATC_CS_C45 0x03 /* Color select bits 4+5 */ 44 45 /* Sequencer registers. */ 46 #define SEQ_IDX_PORT 0x3c4 47 #define SEQ_DATA_PORT 0x3c5 48 49 #define SEQ_RESET 0 50 #define SEQ_RESET_ASYNC 0x1 51 #define SEQ_RESET_SYNC 0x2 52 #define SEQ_CLOCKING_MODE 1 53 #define SEQ_CM_SO 0x20 /* Screen off */ 54 #define SEQ_CM_89 0x01 /* 8/9 dot clock */ 55 #define SEQ_MAP_MASK 2 56 #define SEQ_CHAR_MAP_SELECT 3 57 #define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */ 58 #define SEQ_CMS_SAH_SHIFT 5 59 #define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */ 60 #define SEQ_CMS_SA_SHIFT 2 61 #define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */ 62 #define SEQ_CMS_SBH_SHIFT 4 63 #define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */ 64 #define SEQ_CMS_SB_SHIFT 0 65 #define SEQ_MEMORY_MODE 4 66 #define SEQ_MM_C4 0x08 /* Chain 4 */ 67 #define SEQ_MM_OE 0x04 /* Odd/even */ 68 #define SEQ_MM_EM 0x02 /* Extended memory */ 69 70 /* Graphics controller registers. */ 71 #define GC_IDX_PORT 0x3ce 72 #define GC_DATA_PORT 0x3cf 73 74 #define GC_SET_RESET 0 75 #define GC_ENABLE_SET_RESET 1 76 #define GC_COLOR_COMPARE 2 77 #define GC_DATA_ROTATE 3 78 #define GC_READ_MAP_SELECT 4 79 #define GC_MODE 5 80 #define GC_MODE_OE 0x10 /* Odd/even */ 81 #define GC_MODE_C4 0x04 /* Chain 4 */ 82 83 #define GC_MISCELLANEOUS 6 84 #define GC_MISC_GM 0x01 /* Graphics/alphanumeric */ 85 #define GC_MISC_MM 0x0c /* memory map */ 86 #define GC_MISC_MM_SHIFT 2 87 #define GC_COLOR_DONT_CARE 7 88 #define GC_BIT_MASK 8 89 90 /* CRT controller registers. */ 91 #define CRTC_IDX_MONO_PORT 0x3b4 92 #define CRTC_DATA_MONO_PORT 0x3b5 93 #define CRTC_IDX_COLOR_PORT 0x3d4 94 #define CRTC_DATA_COLOR_PORT 0x3d5 95 96 #define CRTC_HORIZ_TOTAL 0 97 #define CRTC_HORIZ_DISP_END 1 98 #define CRTC_START_HORIZ_BLANK 2 99 #define CRTC_END_HORIZ_BLANK 3 100 #define CRTC_START_HORIZ_RETRACE 4 101 #define CRTC_END_HORIZ_RETRACE 5 102 #define CRTC_VERT_TOTAL 6 103 #define CRTC_OVERFLOW 7 104 #define CRTC_OF_VRS9 0x80 /* VRS bit 9 */ 105 #define CRTC_OF_VRS9_SHIFT 7 106 #define CRTC_OF_VDE9 0x40 /* VDE bit 9 */ 107 #define CRTC_OF_VDE9_SHIFT 6 108 #define CRTC_OF_VRS8 0x04 /* VRS bit 8 */ 109 #define CRTC_OF_VRS8_SHIFT 2 110 #define CRTC_OF_VDE8 0x02 /* VDE bit 8 */ 111 #define CRTC_OF_VDE8_SHIFT 1 112 #define CRTC_PRESET_ROW_SCAN 8 113 #define CRTC_MAX_SCAN_LINE 9 114 #define CRTC_MSL_MSL 0x1f 115 #define CRTC_CURSOR_START 10 116 #define CRTC_CS_CO 0x20 /* Cursor off */ 117 #define CRTC_CS_CS 0x1f /* Cursor start */ 118 #define CRTC_CURSOR_END 11 119 #define CRTC_CE_CE 0x1f /* Cursor end */ 120 #define CRTC_START_ADDR_HIGH 12 121 #define CRTC_START_ADDR_LOW 13 122 #define CRTC_CURSOR_LOC_HIGH 14 123 #define CRTC_CURSOR_LOC_LOW 15 124 #define CRTC_VERT_RETRACE_START 16 125 #define CRTC_VERT_RETRACE_END 17 126 #define CRTC_VRE_MASK 0xf 127 #define CRTC_VERT_DISP_END 18 128 #define CRTC_OFFSET 19 129 #define CRTC_UNDERLINE_LOC 20 130 #define CRTC_START_VERT_BLANK 21 131 #define CRTC_END_VERT_BLANK 22 132 #define CRTC_MODE_CONTROL 23 133 #define CRTC_MC_TE 0x80 /* Timing enable */ 134 #define CRTC_LINE_COMPARE 24 135 136 /* DAC registers */ 137 #define DAC_MASK 0x3c6 138 #define DAC_IDX_RD_PORT 0x3c7 139 #define DAC_IDX_WR_PORT 0x3c8 140 #define DAC_DATA_PORT 0x3c9 141 142 #define VBE_DISPI_INDEX_ID 0x0 143 #define VBE_DISPI_INDEX_XRES 0x1 144 #define VBE_DISPI_INDEX_YRES 0x2 145 #define VBE_DISPI_INDEX_BPP 0x3 146 #define VBE_DISPI_INDEX_ENABLE 0x4 147 #define VBE_DISPI_INDEX_BANK 0x5 148 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 149 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 150 #define VBE_DISPI_INDEX_X_OFFSET 0x8 151 #define VBE_DISPI_INDEX_Y_OFFSET 0x9 152 #define VBE_DISPI_INDEX_VIDEO_MEM_64K 0xa 153 #define VBE_DISPI_DISABLED 0x00 154 #define VBE_DISPI_ENABLED 0x01 155 #define VBE_DISPI_GETCAPS 0x02 156 #define VBE_DISPI_8BIT_DAC 0x20 157 #define VBE_DISPI_LFB_ENABLED 0x40 158 #define VBE_DISPI_NOCLEARMEM 0x80 159 #define VBE_DISPI_ID0 0xB0C0 160 #define VBE_DISPI_ID1 0xB0C1 161 #define VBE_DISPI_ID2 0xB0C2 162 #define VBE_DISPI_ID3 0xB0C3 163 #define VBE_DISPI_ID4 0xB0C4 164 #define VBE_DISPI_ID5 0xB0C5 165 166 struct vga { 167 bool enable; 168 void *dev; 169 struct gfx_ctx *gc; 170 struct surface surf; 171 pthread_t tid; 172 struct { 173 uint16_t id; 174 uint16_t xres; 175 uint16_t yres; 176 uint16_t bpp; 177 uint16_t enable; 178 uint16_t bank; 179 uint16_t virt_width; 180 uint16_t virt_height; 181 uint16_t x_offset; 182 uint16_t y_offset; 183 uint16_t video_memory_64k; 184 } __attribute__((packed)) vberegs; 185 }; 186 187 void *vga_init(struct gfx_ctx *gc, int io_only); 188 void vga_render(struct gfx_ctx *gc, void *arg); 189 int vga_port_in_handler(struct vmctx *ctx, int in, int port, int bytes, 190 uint8_t *val, void *arg); 191 int vga_port_out_handler(struct vmctx *ctx, int in, int port, int bytes, 192 uint8_t val, void *arg); 193 void vga_ioport_write(struct vmctx *ctx, int vcpu, struct vga *vga, 194 uint64_t offset, int size, uint64_t value); 195 uint64_t vga_ioport_read(struct vmctx *ctx, int vcpu, struct vga *vga, 196 uint64_t offset, int size); 197 void vga_vbe_write(struct vmctx *ctx, int vcpu, struct vga *vga, 198 uint64_t offset, int size, uint64_t value); 199 uint64_t vga_vbe_read(struct vmctx *ctx, int vcpu, struct vga *vga, 200 uint64_t offset, int size); 201 202 void vga_deinit(struct vga *vga); 203 #endif /* _VGA_H_ */ 204