1 /*- 2 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _XHCI_H_ 30 #define _XHCI_H_ 31 32 #define PCI_USBREV 0x60 /* USB protocol revision */ 33 34 enum { /* dsc_slotstate */ 35 XHCI_ST_DISABLED, 36 XHCI_ST_ENABLED, 37 XHCI_ST_DEFAULT, 38 XHCI_ST_ADDRESSED, 39 XHCI_ST_CONFIGURED, 40 XHCI_ST_MAX 41 }; 42 43 enum { 44 XHCI_ST_SLCTX_DISABLED, 45 XHCI_ST_SLCTX_DEFAULT, 46 XHCI_ST_SLCTX_ADDRESSED, 47 XHCI_ST_SLCTX_CONFIGURED 48 }; 49 50 enum { 51 XHCI_ST_EPCTX_DISABLED, 52 XHCI_ST_EPCTX_RUNNING, 53 XHCI_ST_EPCTX_HALTED, 54 XHCI_ST_EPCTX_STOPPED, 55 XHCI_ST_EPCTX_ERROR 56 }; 57 58 #define XHCI_MAX_VIRT_PORTS MIN(USB_MAX_DEVICES, 128) 59 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 60 #define XHCI_MAX_SCRATCHPADS 32 61 #define XHCI_MAX_EVENTS (16 * 13) 62 #define XHCI_MAX_COMMANDS (16 * 1) 63 #define XHCI_MAX_RSEG 1 64 #define XHCI_MAX_TRANSFERS 4 65 #if USB_MAX_EP_STREAMS == 8 66 #define XHCI_MAX_STREAMS 8 67 #define XHCI_MAX_STREAMS_LOG 3 68 #elif USB_MAX_EP_STREAMS == 1 69 #define XHCI_MAX_STREAMS 1 70 #define XHCI_MAX_STREAMS_LOG 0 71 #else 72 #error "The USB_MAX_EP_STREAMS value is not supported." 73 #endif 74 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 75 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 76 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 77 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 78 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 79 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 80 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 81 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 82 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 83 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 84 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 85 #define XHCI_TRB_ALIGN 16 /* bytes */ 86 #define XHCI_TD_ALIGN 64 /* bytes */ 87 #define XHCI_PAGE_SIZE 4096 /* bytes */ 88 89 /* xHCI extended capability supported protocol fileds */ 90 #define DEFINE_EXCP_PROT(name, next_ptr, revmaj, portoff, portcnt) \ 91 struct pci_xhci_excap_prot excap_##name = { \ 92 { \ 93 .cap_id = XHCI_ID_PROTOCOLS, \ 94 .cap_ptr = next_ptr \ 95 }, \ 96 .rev_min = 0x00, \ 97 .rev_maj = revmaj, \ 98 .string = "USB"#revmaj, \ 99 .port_off = portoff, \ 100 .port_cnt = portcnt, \ 101 .psic_prot_def = 0x00, \ 102 .reserve = 0x00 \ 103 } 104 105 /* Intel ApolloLake xHCI extended capability for DRD. */ 106 #define DEFINE_EXCP_VENDOR_DRD(capid, next_ptr, reg0, reg1) \ 107 struct pci_xhci_excap_drd_apl excap_drd_apl = { \ 108 { \ 109 .cap_id = capid, \ 110 .cap_ptr = next_ptr \ 111 }, \ 112 .padding = {0}, \ 113 .drdcfg0 = reg0, \ 114 .drdcfg1 = reg1 \ 115 } 116 117 struct xhci_slot_ctx { 118 volatile uint32_t dwSctx0; 119 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 120 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 121 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 122 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 123 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 124 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 125 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 126 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 127 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 128 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 129 volatile uint32_t dwSctx1; 130 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 131 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 132 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 133 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 134 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 135 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 136 volatile uint32_t dwSctx2; 137 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 138 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 139 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 140 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 141 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 142 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 143 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 144 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 145 volatile uint32_t dwSctx3; 146 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 147 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 148 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 149 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 150 volatile uint32_t dwSctx4; 151 volatile uint32_t dwSctx5; 152 volatile uint32_t dwSctx6; 153 volatile uint32_t dwSctx7; 154 }; 155 156 struct xhci_endp_ctx { 157 volatile uint32_t dwEpCtx0; 158 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 159 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 160 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 161 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 162 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 163 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 164 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 165 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 166 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 167 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 168 volatile uint32_t dwEpCtx1; 169 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 170 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 171 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 172 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 173 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 174 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 175 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 176 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 177 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 178 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 179 volatile uint64_t qwEpCtx2; 180 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 181 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 182 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 183 volatile uint32_t dwEpCtx4; 184 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 185 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 186 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 187 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 188 volatile uint32_t dwEpCtx5; 189 volatile uint32_t dwEpCtx6; 190 volatile uint32_t dwEpCtx7; 191 }; 192 193 #define XHCI_EPTYPE_INVALID 0 194 #define XHCI_EPTYPE_ISOC_OUT 1 195 #define XHCI_EPTYPE_BULK_OUT 2 196 #define XHCI_EPTYPE_INT_OUT 3 197 #define XHCI_EPTYPE_CTRL 4 198 #define XHCI_EPTYPE_ISOC_IN 5 199 #define XHCI_EPTYPE_BULK_IN 6 200 #define XHCI_EPTYPE_INT_IN 7 201 202 struct xhci_input_ctx { 203 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 204 volatile uint32_t dwInCtx0; 205 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 206 volatile uint32_t dwInCtx1; 207 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 208 volatile uint32_t dwInCtx2; 209 volatile uint32_t dwInCtx3; 210 volatile uint32_t dwInCtx4; 211 volatile uint32_t dwInCtx5; 212 volatile uint32_t dwInCtx6; 213 volatile uint32_t dwInCtx7; 214 }; 215 216 struct xhci_input_dev_ctx { 217 struct xhci_input_ctx ctx_input; 218 union { 219 struct xhci_slot_ctx u_slot; 220 struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS]; 221 } ctx_dev_slep; 222 }; 223 224 struct xhci_dev_ctx { 225 union { 226 struct xhci_slot_ctx u_slot; 227 struct xhci_endp_ctx u_ep[XHCI_MAX_ENDPOINTS]; 228 } ctx_dev_slep; 229 } __aligned(XHCI_DEV_CTX_ALIGN); 230 #define ctx_slot ctx_dev_slep.u_slot 231 #define ctx_ep ctx_dev_slep.u_ep 232 233 struct xhci_stream_ctx { 234 volatile uint64_t qwSctx0; 235 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 236 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 237 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 238 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 239 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 240 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 241 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 242 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 243 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 244 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 245 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 246 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 247 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 248 volatile uint32_t dwSctx2; 249 volatile uint32_t dwSctx3; 250 }; 251 252 struct xhci_trb { 253 volatile uint64_t qwTrb0; 254 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 255 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 256 volatile uint32_t dwTrb2; 257 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 258 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 259 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 260 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 261 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 262 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 263 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 264 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 265 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 266 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 267 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 268 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 269 270 volatile uint32_t dwTrb3; 271 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 272 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 273 #define XHCI_TRB_3_CYCLE_BIT (1U << 0) 274 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 275 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 276 #define XHCI_TRB_3_ISP_BIT (1U << 2) 277 #define XHCI_TRB_3_ED_BIT (1U << 2) 278 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 279 #define XHCI_TRB_3_CHAIN_BIT (1U << 4) 280 #define XHCI_TRB_3_IOC_BIT (1U << 5) 281 #define XHCI_TRB_3_IDT_BIT (1U << 6) 282 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 283 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 284 #define XHCI_TRB_3_BEI_BIT (1U << 9) 285 #define XHCI_TRB_3_DCEP_BIT (1U << 9) 286 #define XHCI_TRB_3_PRSV_BIT (1U << 9) 287 #define XHCI_TRB_3_BSR_BIT (1U << 9) 288 #define XHCI_TRB_3_TRT_MASK (3U << 16) 289 #define XHCI_TRB_3_TRT_NONE (0U << 16) 290 #define XHCI_TRB_3_TRT_OUT (2U << 16) 291 #define XHCI_TRB_3_TRT_IN (3U << 16) 292 #define XHCI_TRB_3_DIR_IN (1U << 16) 293 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 294 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 295 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 296 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 297 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 298 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 299 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 300 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 301 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 302 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 303 304 /* Commands */ 305 #define XHCI_TRB_TYPE_RESERVED 0x00 306 #define XHCI_TRB_TYPE_NORMAL 0x01 307 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 308 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 309 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 310 #define XHCI_TRB_TYPE_ISOCH 0x05 311 #define XHCI_TRB_TYPE_LINK 0x06 312 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 313 #define XHCI_TRB_TYPE_NOOP 0x08 314 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 315 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 316 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 317 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 318 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 319 #define XHCI_TRB_TYPE_RESET_EP 0x0E 320 #define XHCI_TRB_TYPE_STOP_EP 0x0F 321 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 322 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 323 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 324 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 325 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 326 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 327 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 328 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 329 330 /* Events */ 331 #define XHCI_TRB_EVENT_TRANSFER 0x20 332 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 333 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 334 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 335 #define XHCI_TRB_EVENT_DOORBELL 0x24 336 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 337 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 338 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 339 340 /* Error codes */ 341 #define XHCI_TRB_ERROR_INVALID 0x00 342 #define XHCI_TRB_ERROR_SUCCESS 0x01 343 #define XHCI_TRB_ERROR_DATA_BUF 0x02 344 #define XHCI_TRB_ERROR_BABBLE 0x03 345 #define XHCI_TRB_ERROR_XACT 0x04 346 #define XHCI_TRB_ERROR_TRB 0x05 347 #define XHCI_TRB_ERROR_STALL 0x06 348 #define XHCI_TRB_ERROR_RESOURCE 0x07 349 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 350 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 351 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 352 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 353 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 354 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D 355 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 356 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 357 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 358 #define XHCI_TRB_ERROR_PARAMETER 0x11 359 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 360 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 361 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 362 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 363 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 364 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 365 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 366 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 367 #define XHCI_TRB_ERROR_STOPPED 0x1A 368 #define XHCI_TRB_ERROR_LENGTH 0x1B 369 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D 370 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 371 #define XHCI_TRB_ERROR_EVENT_LOST 0x20 372 #define XHCI_TRB_ERROR_UNDEFINED 0x21 373 #define XHCI_TRB_ERROR_INVALID_SID 0x22 374 #define XHCI_TRB_ERROR_SEC_BW 0x23 375 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 376 } __aligned(8); 377 378 /* 379 * The Block Event Interrupt (BEI) bit in the TRB descriptor could 380 * delay the triggering of interrupt. For most OSes, the native 381 * driver for xHCI will use this bit to optimize the IO performence, 382 * due to reduction of number of interrupts. 383 * 384 * But in Linux, the native xHCI driver for Intel brand controller 385 * doesn't use this bit. It is fine for the native scenario due to 386 * most work is completed by hardware. But in virtualization scenario, 387 * it is almost impossible to support heavy data IO such as high 388 * resolution video recording (ISOC transfer). 389 * 390 * Hence, this issue is solved by a 'quirk' when the intel hardware is 391 * emulated (when vendor id is set as 0x8086). For other cases, a 392 * virtal hardware called 'ACRN xHCI' is emulated, and both Linux and 393 * Windows will use BEI bit by default. 394 */ 395 #define XHCI_QUIRK_INTEL_ISOCH_NO_BEI (1 << 0) 396 397 struct xhci_dev_endpoint_trbs { 398 struct xhci_trb trb[(XHCI_MAX_STREAMS * 399 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 400 }; 401 402 403 struct xhci_erst { 404 volatile uint64_t qwRingSegBase; 405 volatile uint32_t dwRingSegSize; 406 volatile uint32_t dwRingSegRsv; 407 }; 408 409 #endif /* _XHCI_H_ */ 410