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Searched refs:XHCI_STS_SSS (Results 1 – 2 of 2) sorted by relevance

/devicemodel/include/
A Dxhcireg.h93 #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ macro
/devicemodel/hw/pci/
A Dxhci.c3610 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS| in pci_xhci_hostop_write()

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