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/devicemodel/include/
A Dpci_core.h80 struct pci_vdev *pi, int offset,
83 struct pci_vdev *pi, int offset,
92 uint64_t offset, int size);
415 if (offset > PCI_REGMAX) { in pci_set_cfgdata8()
419 *(uint8_t *)(dev->cfgdata + offset) = val; in pci_set_cfgdata8()
432 if ((offset > PCI_REGMAX - 1) || (offset & 1) != 0) { in pci_set_cfgdata16()
436 *(uint16_t *)(dev->cfgdata + offset) = val; in pci_set_cfgdata16()
449 if ((offset > PCI_REGMAX - 3) || (offset & 3) != 0) { in pci_set_cfgdata32()
467 if (offset > PCI_REGMAX) { in pci_get_cfgdata8()
485 if ((offset > PCI_REGMAX - 1) || (offset & 1) != 0) { in pci_get_cfgdata16()
[all …]
A Dvirtio.h707 int baridx, uint64_t offset, int size);
724 int baridx, uint64_t offset, int size, uint64_t value);
747 uint64_t offset, int size, uint64_t value);
749 uint64_t offset, int size, uint64_t value);
751 uint64_t offset, int size, uint64_t value);
753 struct pci_vdev *dev, uint64_t offset, int size);
755 struct pci_vdev *dev, uint64_t offset, int size);
757 struct pci_vdev *dev, uint64_t offset, int size);
A Dvga.h194 uint64_t offset, int size, uint64_t value);
196 uint64_t offset, int size);
198 uint64_t offset, int size, uint64_t value);
200 uint64_t offset, int size);
A Duart_core.h41 uint8_t uart_read(struct uart_vdev *uart, int offset);
42 void uart_write(struct uart_vdev *uart, int offset, uint8_t value);
/devicemodel/hw/pci/virtio/
A Dvirtio.c864 if (cr->offset == offset) in virtio_find_cr()
866 if (cr->offset < offset) in virtio_find_cr()
878 offset); in virtio_find_legacy_cr()
885 offset); in virtio_find_modern_cr()
956 switch (offset) { in virtio_pci_legacy_read()
1097 switch (offset) { in virtio_pci_legacy_write()
1295 .cap.offset = 0, in virtio_set_modern_pio_bar()
1409 switch (offset) { in virtio_common_cfg_read()
1936 offset, size); in virtio_pci_read()
1940 offset, size); in virtio_pci_read()
[all …]
A Dvirtio_gpio.c180 uint8_t offset; member
439 offset)); in gpio_get_value()
576 offset -= cfg_size; in virtio_gpio_cfgwrite()
577 if (offset < 0 || offset >= GPIO_PIO_SIZE) { in virtio_gpio_cfgwrite()
595 if (offset < 0 || offset >= cfg_size + GPIO_PIO_SIZE) { in virtio_gpio_cfgread()
745 line->offset = i; in native_gpio_open_chip()
792 int offset; in native_gpio_find_line() local
801 if (offset < 0) { in native_gpio_find_line()
1569 line->offset)); in print_gpio_info()
1609 req->offset, in print_virtio_gpio_info()
[all …]
A Dvirtio_gpu.c274 uint64_t offset; member
494 ptr = (uint8_t *)&gpu->cfg + offset; in virtio_gpu_cfgread()
507 ptr = (uint8_t *)&gpu->cfg + offset; in virtio_gpu_cfgwrite()
1822 cap.offset = VIRTIO_CAP_DEVICE_OFFSET; in virtio_gpu_init()
1944 uint64_t offset, int size) in virtio_gpu_edid_read() argument
1951 p = (uint8_t *)gpu->edid + offset; in virtio_gpu_edid_read()
1984 if ((offset >= 0) && (offset <= VIRTIO_GPU_EDID_SIZE)) { in virtio_gpu_write()
2016 offset -= VIRTIO_CAP_DEVICE_OFFSET; in virtio_gpu_write()
2021 offset -= VIRTIO_CAP_NOTIFY_OFFSET; in virtio_gpu_write()
2043 if ((offset >= 0) && (offset <= VIRTIO_GPU_EDID_SIZE)) { in virtio_gpu_read()
[all …]
A Dvirtio_hdcp.c225 int offset = 0; in SendMessage() local
229 ssize_t count = send(fd, &data[offset], bytesRemaining, MSG_NOSIGNAL); in SendMessage()
242 offset += count; in SendMessage()
252 int offset = 0; in GetMessage() local
256 count = read(fd, &data[offset], bytesRemaining); in GetMessage()
275 offset += count; in GetMessage()
A Dvirtio_block.c272 io->req.offset = vbh->sector * DEV_BSIZE; in virtio_blk_proc()
320 io->req.offset)); in virtio_blk_proc()
760 virtio_blk_cfgwrite(void *vdev, int offset, int size, uint32_t value) in virtio_blk_cfgwrite() argument
766 ptr = (uint8_t *)blkcfg + offset; in virtio_blk_cfgwrite()
768 if ((offset == offsetof(struct virtio_blk_config, writeback)) in virtio_blk_cfgwrite()
781 DPRINTF(("virtio_blk: write to readonly reg %d\n\r", offset)); in virtio_blk_cfgwrite()
786 virtio_blk_cfgread(void *vdev, int offset, int size, uint32_t *retval) in virtio_blk_cfgread() argument
792 ptr = (uint8_t *)&blk->cfg + offset; in virtio_blk_cfgread()
/devicemodel/hw/
A Dvga.c190 int offset; in vga_get_pixel() local
223 int offset; in vga_render_graphics() local
286 int offset; in vga_render_text() local
319 int offset; in vga_mem_rd_handler() local
321 offset = addr; in vga_mem_rd_handler()
388 offset &= ~1; in vga_mem_rd_handler()
406 int offset; in vga_mem_wr_handler() local
408 offset = addr; in vga_mem_wr_handler()
650 offset &= ~1; in vga_mem_wr_handler()
1374 port = offset; in vga_ioport_write()
[all …]
A Dblock_if.c233 off = breq->offset; in blockif_enqueue()
243 if (tbe->block == breq->offset) in blockif_enqueue()
248 if (tbe->block == breq->offset) in blockif_enqueue()
291 if (tbe->req->offset == be->block) in blockif_complete()
672 bytes_read = preadv(fd, b_iov, 1, offset); in blockif_read_head_or_tail_area()
797 off_t offset; in blockif_proc() local
810 offset = info->aligned_dn_start; in blockif_proc()
815 offset = br->offset + bc->sub_file_start_lba; in blockif_proc()
1052 off_t offset; in iou_submit_sqe() local
1064 offset = info->aligned_dn_start; in iou_submit_sqe()
[all …]
/devicemodel/hw/pci/
A Dwdt_i6300esb.c202 int offset, int bytes, uint32_t *rv) in pci_wdt_cfg_read() argument
208 if (offset == ESB_LOCK_REG && bytes == 1) { in pci_wdt_cfg_read()
220 int offset, int bytes, uint32_t val) in pci_wdt_cfg_write() argument
226 __func__, offset, bytes, val); in pci_wdt_cfg_write()
259 if (offset == ESB_GIS_REG) { in pci_wdt_bar_write()
270 } else if (offset == ESB_RELOAD_REG) { in pci_wdt_bar_write()
294 if (offset == ESB_TIMER1_REG) in pci_wdt_bar_write()
296 else if (offset == ESB_TIMER2_REG) in pci_wdt_bar_write()
305 int baridx, uint64_t offset, int size) in pci_wdt_bar_read() argument
311 if (offset == ESB_GIS_REG) { in pci_wdt_bar_read()
[all …]
A Dpci_util.c48 int offset = 0; in pci_find_ext_cap() local
51 offset = PCIR_EXTCAP; in pci_find_ext_cap()
55 pci_device_cfg_read_u32(pdev, &data, offset); in pci_find_ext_cap()
60 offset = PCI_EXTCAP_NEXTPTR(data); in pci_find_ext_cap()
61 } while (offset != 0); in pci_find_ext_cap()
63 return offset; in pci_find_ext_cap()
A Dnpk.c152 static inline uint32_t *offset2reg(uint64_t offset) in offset2reg() argument
160 if (offset >= regs->base && offset < regs->base + regs->size) { in offset2reg()
161 reg = regs->data.u32 + ((offset - regs->base) >> 2); in offset2reg()
307 npk_csr[d->csr].data.u32[d->offset >> 2] = d->default_val; in pci_npk_init()
336 int baridx, uint64_t offset, int size, uint64_t value) in pci_npk_write() argument
342 if (baridx != 0 || (offset & 0x3) || size != 4) in pci_npk_write()
346 reg = offset2reg(offset); in pci_npk_write()
352 int baridx, uint64_t offset, int size) in pci_npk_read() argument
356 DPRINTF(("R %d +0x%lx[%d] val 0x%x\n", baridx, offset, size, val)); in pci_npk_read()
358 if (baridx != 0 || (offset & 0x3) || size != 4) in pci_npk_read()
[all …]
A Dcore.c502 uint64_t offset; in pci_emul_io_handler() local
529 uint64_t offset; in pci_emul_mem_handler() local
1096 int rc, offset = 0; in pci_access_msi() local
1108 offset = offset + msi_cap; in pci_access_msi()
1110 offset = offset + msi_cap - 0x04; in pci_access_msi()
1288 off = offset - capoff; in msixcap_cfgwrite()
1403 if (offset >= capoff && offset < nextoff) in pci_emul_capwrite()
1415 if (offset == capoff || offset == capoff + 1) { in pci_emul_capwrite()
1418 offset += 2; in pci_emul_capwrite()
1448 if (offset >= CAP_START_OFFSET && offset <= dev->capend) in pci_emul_iscap()
[all …]
A Dlpc.c156 int offset; in lpc_uart_io_handler() local
159 offset = port - lpc_uart->iobase; in lpc_uart_io_handler()
164 *eax = uart_read(lpc_uart->uart, offset); in lpc_uart_io_handler()
166 uart_write(lpc_uart->uart, offset, *eax); in lpc_uart_io_handler()
170 *eax = uart_read(lpc_uart->uart, offset); in lpc_uart_io_handler()
171 *eax |= uart_read(lpc_uart->uart, offset + 1) << 8; in lpc_uart_io_handler()
173 uart_write(lpc_uart->uart, offset, *eax); in lpc_uart_io_handler()
174 uart_write(lpc_uart->uart, offset + 1, *eax >> 8); in lpc_uart_io_handler()
410 int baridx, uint64_t offset, int size, uint64_t value) in pci_lpc_write() argument
416 int baridx, uint64_t offset, int size) in pci_lpc_read() argument
A Dxhci.c389 uint64_t offset; member
1314 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ; in pci_xhci_portregs_write()
1325 switch (offset) { in pci_xhci_portregs_write()
3446 offset = (offset - xdev->dboff) / sizeof(uint32_t); in pci_xhci_dbregs_write()
3449 offset, value); in pci_xhci_dbregs_write()
3461 if (offset == 0) in pci_xhci_dbregs_write()
3555 offset); in pci_xhci_rtsregs_write()
3579 offset = (offset - 0x3F0) % 0x10; in pci_xhci_portregs_read()
3796 offset = (offset - XHCI_CAPLEN); in pci_xhci_hostop_read()
3915 offset); in pci_xhci_excap_read()
[all …]
A Divshmem.c176 int baridx, uint64_t offset, int size, uint64_t value) in pci_ivshmem_write() argument
179 __func__, baridx, offset, value); in pci_ivshmem_write()
182 switch (offset) { in pci_ivshmem_write()
196 __func__, offset); in pci_ivshmem_write()
204 int baridx, uint64_t offset, int size) in pci_ivshmem_read() argument
209 __func__, baridx, offset, size); in pci_ivshmem_read()
212 switch (offset) { in pci_ivshmem_read()
230 __func__, offset); in pci_ivshmem_read()
A Dahci.c313 offset = 0x40; in ahci_write_fis()
318 offset = 0x58; in ahci_write_fis()
323 offset = 0x20; in ahci_write_fis()
2068 offset = (offset - AHCI_OFFSET) % AHCI_STEP; in pci_ahci_port_write()
2143 offset); in pci_ahci_port_write()
2174 offset, value); in pci_ahci_host_write()
2182 offset); in pci_ahci_host_write()
2229 offset); in pci_ahci_write()
2262 offset, value); in pci_ahci_host_read()
2274 offset = (offset - AHCI_OFFSET) % AHCI_STEP; in pci_ahci_port_read()
[all …]
A Duart.c69 int baridx, uint64_t offset, int size, uint64_t value) in pci_uart_write() argument
72 uart_write(dev->arg, offset, value); in pci_uart_write()
77 int baridx, uint64_t offset, int size) in pci_uart_read() argument
82 val = uart_read(dev->arg, offset); in pci_uart_read()
A Dptm.c69 int offset = 0; in add_vroot_port() local
101 offset = pci_find_cap(root_port, PCIY_EXPRESS); in add_vroot_port()
102 pci_device_cfg_read_u32(root_port, &dev_cap, offset + PCIER_DEVICE_CAP); in add_vroot_port()
/devicemodel/hw/platform/
A Dhpet.c698 int offset, i; in vhpet_mmio_write() local
700 offset = gpa - VHPET_BASE; in vhpet_mmio_write()
729 if (offset == HPET_CONFIG || offset == HPET_CONFIG + 4) { in vhpet_mmio_write()
759 if (offset == HPET_ISR || offset == HPET_ISR + 4) { in vhpet_mmio_write()
771 if (offset == HPET_MAIN_COUNTER || offset == HPET_MAIN_COUNTER + 4) { in vhpet_mmio_write()
848 int offset, i; in vhpet_mmio_read() local
864 if (offset == HPET_CAPABILITIES || offset == HPET_CAPABILITIES + 4) { in vhpet_mmio_read()
869 if (offset == HPET_CONFIG || offset == HPET_CONFIG + 4) { in vhpet_mmio_read()
874 if (offset == HPET_ISR || offset == HPET_ISR + 4) { in vhpet_mmio_read()
879 if (offset == HPET_MAIN_COUNTER || offset == HPET_MAIN_COUNTER + 4) { in vhpet_mmio_read()
[all …]
A Drtc.c881 offset == RTC_CENTURY || in vrtc_nvram_write()
882 offset >= sizeof(struct rtcdev)) { in vrtc_nvram_write()
889 ptr[offset] = value; in vrtc_nvram_write()
919 return ((offset == RTC_SEC) || (offset == RTC_MIN) || (offset == RTC_HRS) || (offset == RTC_DAY) in vrtc_is_time_register()
920 || (offset == RTC_MONTH) || (offset == RTC_YEAR) || (offset == RTC_CENTURY)); in vrtc_is_time_register()
931 int error, offset; in vrtc_data_handler() local
939 offset = vrtc->addr; in vrtc_data_handler()
956 if (offset < 10 || offset == RTC_CENTURY) in vrtc_data_handler()
960 if (offset == 12) { in vrtc_data_handler()
969 *eax = *((uint8_t *)rtc + offset); in vrtc_data_handler()
[all …]
/devicemodel/core/
A Dhugetlb.c210 size_t offset, size_t skip, char **addr_out) in mmap_hugetlbfs_from_level() argument
226 addr = mmap(ctx->baseaddr + offset, len, PROT_READ | PROT_WRITE, in mmap_hugetlbfs_from_level()
235 mmap_mem_regions[mem_idx].gpa_start = offset; in mmap_hugetlbfs_from_level()
236 mmap_mem_regions[mem_idx].gpa_end = offset + len; in mmap_hugetlbfs_from_level()
258 static int mmap_hugetlbfs(struct vmctx *ctx, size_t offset, in mmap_hugetlbfs() argument
270 ret = mmap_hugetlbfs_from_level(ctx, level, len, offset, skip, addr); in mmap_hugetlbfs()
279 offset += len; in mmap_hugetlbfs()
868 uint64_t offset; in vm_find_memfd_region() local
882 offset = gpa - mmap_region->gpa_start; in vm_find_memfd_region()
884 ret_region->fd_offset = offset + mmap_region->fd_offset; in vm_find_memfd_region()
/devicemodel/hw/platform/rpmb/
A Datt_keybox.c78 req.offset = 0; in get_attkb_size()
150 req.offset = 0; in read_attkb()
155 req.offset = bytes_read; in read_attkb()

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