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Searched refs:reg (Results 1 – 12 of 12) sorted by relevance

/devicemodel/hw/pci/
A Dirq.c57 uint8_t reg; member
72 pirq_valid_irq(int reg) in pirq_valid_irq() argument
74 if (reg & PIRQ_DIS) in pirq_valid_irq()
76 return IRQ_PERMITTED(reg & PIRQ_IRQ); in pirq_valid_irq()
85 return pirqs[pin - 1].reg; in pirq_read()
98 if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) { in pirq_write()
101 pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ); in pirq_write()
129 pirqs[i].reg = PIRQ_DIS; in pci_irq_init()
178 if (pirqs[best_pin].reg == PIRQ_DIS) { in pirq_alloc_pin()
193 pirqs[best_pin].reg = best_irq; in pirq_alloc_pin()
[all …]
A Dnpk.c154 uint32_t *reg = NULL, i; in offset2reg() local
161 reg = regs->data.u32 + ((offset - regs->base) >> 2); in offset2reg()
166 return reg; in offset2reg()
338 uint32_t *reg; in pci_npk_write() local
346 reg = offset2reg(offset); in pci_npk_write()
347 if (reg) in pci_npk_write()
348 *reg = (uint32_t)value; in pci_npk_write()
354 uint32_t *reg, val = 0; in pci_npk_read() local
362 reg = offset2reg(offset); in pci_npk_read()
363 if (reg) in pci_npk_read()
[all …]
A Dptm.c45 get_ptm_reg_value(struct pci_device *pdev, int reg) in get_ptm_reg_value() argument
56 pci_device_cfg_read_u32(pdev, &reg_val, pos + reg); in get_ptm_reg_value()
A Dpassthrough.c75 read_config(struct pci_device *phys_dev, long reg, int width) in read_config() argument
81 pci_device_cfg_read_u8(phys_dev, (uint8_t *)&temp, reg); in read_config()
84 pci_device_cfg_read_u16(phys_dev, (uint16_t *)&temp, reg); in read_config()
87 pci_device_cfg_read_u32(phys_dev, &temp, reg); in read_config()
98 write_config(struct pci_device *phys_dev, long reg, int width, uint32_t data) in write_config() argument
104 temp = pci_device_cfg_write_u8(phys_dev, data, reg); in write_config()
107 temp = pci_device_cfg_write_u16(phys_dev, data, reg); in write_config()
110 temp = pci_device_cfg_write_u32(phys_dev, data, reg); in write_config()
304 bar.reg = PCIR_BAR(i); in cfginitbar()
306 bar.base = read_config(ptdev->phys_dev, bar.reg, 4); in cfginitbar()
A Dxhci.c1144 struct pci_xhci_portregs *reg; in pci_xhci_change_port() local
1146 reg = XHCI_PORTREG_PTR(xdev, port); in pci_xhci_change_port()
1148 reg->portsc &= ~(XHCI_PS_CCS | XHCI_PS_PED); in pci_xhci_change_port()
1149 reg->portsc |= (XHCI_PS_CSC | in pci_xhci_change_port()
1153 reg->portsc = XHCI_PS_CCS | XHCI_PS_PP | XHCI_PS_CSC; in pci_xhci_change_port()
1154 reg->portsc |= XHCI_PS_SPEED_SET(speed); in pci_xhci_change_port()
1156 reg->portsc |= XHCI_PS_PED; in pci_xhci_change_port()
1157 reg->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0); in pci_xhci_change_port()
1159 reg->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL); in pci_xhci_change_port()
1182 UPRINTF(LDBG, "%s: port %d:%08X\r\n", __func__, port, reg->portsc); in pci_xhci_change_port()
A Dcore.c2565 int func, int reg, int bytes, int *value) in emulate_pci_cfgrw() argument
2567 pci_cfgrw(ctx, vcpu, in, bus, slot, func, reg, in emulate_pci_cfgrw()
/devicemodel/hw/
A Duart_core.c545 reg = uart->dll; in uart_read()
550 reg = uart->dlh; in uart_read()
560 reg = uart->ier; in uart_read()
575 reg = iir; in uart_read()
578 reg = uart->lcr; in uart_read()
581 reg = uart->mcr; in uart_read()
593 reg = uart->lsr; in uart_read()
602 reg = uart->msr; in uart_read()
606 reg = uart->scr; in uart_read()
609 reg = 0xFF; in uart_read()
[all …]
/devicemodel/hw/pci/virtio/
A Dvirtio_gpio.c592 uint32_t reg; in virtio_gpio_cfgread() local
602 reg = gpio_pio_read(gpio, (offset - cfg_size) >> 2); in virtio_gpio_cfgread()
603 memcpy(retval, &reg, size); in virtio_gpio_cfgread()
1497 value = reg & PIO_GPIO_VALUE_MASK; in gpio_pio_write()
1509 n, reg, value, dir, mode, config)); in gpio_pio_write()
1525 uint32_t reg = 0; in gpio_pio_read() local
1534 reg = line->value; in gpio_pio_read()
1536 reg |= ((line->config << PIO_GPIO_CONFIG_OFFSET) & in gpio_pio_read()
1539 reg |= 1 << PIO_GPIO_MODE_OFFSET; in gpio_pio_read()
1541 DPRINTF(("pio read n %d, reg 0x%X\n", n, reg)); in gpio_pio_read()
[all …]
/devicemodel/include/
A Dpciio.h108 int reg; /* configuration register to examine */ member
115 int reg; /* starting address of BAR */ member
A Dpcireg.h641 #define PCIM_EA_SEC_NR(reg) ((reg) & 0xff) argument
642 #define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff) argument
A Dpci_core.h395 int slot, int func, int reg, int bytes, int *value);
/devicemodel/core/
A Dmain.c429 io_req->reqs.pci_request.reg, in vmexit_pci_emul()
437 io_req->reqs.pci_request.reg); in vmexit_pci_emul()

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