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Searched refs:uint64_t (Results 1 – 25 of 70) sorted by relevance

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/devicemodel/include/
A Dpci_core.h89 uint64_t offset, int size, uint64_t value);
113 uint64_t size;
114 uint64_t addr;
121 uint64_t addr;
160 uint64_t addr;
161 uint64_t msg_data;
258 uint64_t start;
259 uint64_t end;
337 uint64_t size);
388 uint64_t value);
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A Dvirtio.h353 uint64_t device_caps; /**< device capabilities */
398 void (*apply_features)(void *, uint64_t);
400 void (*set_status)(void *, uint64_t);
707 int baridx, uint64_t offset, int size);
724 int baridx, uint64_t offset, int size, uint64_t value);
747 uint64_t offset, int size, uint64_t value);
749 uint64_t offset, int size, uint64_t value);
751 uint64_t offset, int size, uint64_t value);
753 struct pci_vdev *dev, uint64_t offset, int size);
755 struct pci_vdev *dev, uint64_t offset, int size);
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A Dtimer.h16 void (*callback)(void *, uint64_t);
21 acrn_timer_init(struct acrn_timer *timer, void (*cb)(void *, uint64_t), void *param);
34 static inline uint64_t
37 uint64_t tv_sec_ticks, tv_nsec_ticks; in ts_to_ticks()
46 ticks_to_ts(const uint32_t freq, const uint64_t ticks, in ticks_to_ts()
49 uint64_t ns; in ticks_to_ts()
A Dsegments.h126 uint64_t gd_looffset:16; /* gate offset (lsb) */
127 uint64_t gd_selector:16; /* gate segment selector */
128 uint64_t gd_ist:3; /* IST table index */
129 uint64_t gd_xx:5; /* unused */
130 uint64_t gd_type:5; /* segment type */
131 uint64_t gd_dpl:2; /* segment descriptor priority level */
132 uint64_t gd_p:1; /* segment descriptor present */
133 uint64_t gd_hioffset:48; /* gate offset (msb) */
134 uint64_t sd_xx1:32;
A Dtypes.h20 typedef uint64_t vm_paddr_t;
21 typedef uint64_t vm_ooffset_t;
22 typedef uint64_t cap_ioctl_t;
91 flsl(uint64_t mask) in flsl()
104 bitmap_weight(uint64_t bits) in bitmap_weight()
120 build_bitmap_clear(bitmap_clear_nolock, "q", uint64_t, "")
129 static inline uint16_t ffs64(uint64_t value) in ffs64()
178 (((uint64_t)((w)[4])) << 32) | \
179 (((uint64_t)((w)[5])) << 40) | \
180 (((uint64_t)((w)[6])) << 48) | \
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A Dvmmapi.h53 uint64_t highmem_gpa_base;
82 uint64_t msg;
83 uint64_t addr;
92 uint64_t fd_offset;
103 struct vmctx *vm_create(const char *name, uint64_t req_buf, int* vcpu_num);
110 int vm_setup_asyncio(struct vmctx *ctx, uint64_t base);
121 uint64_t vma, int prot);
134 int vm_lapic_msi(struct vmctx *ctx, uint64_t addr, uint64_t msg);
152 uint64_t vm_get_cpu_affinity_dm(void);
A Dvga.h194 uint64_t offset, int size, uint64_t value);
195 uint64_t vga_ioport_read(struct vmctx *ctx, int vcpu, struct vga *vga,
196 uint64_t offset, int size);
198 uint64_t offset, int size, uint64_t value);
199 uint64_t vga_vbe_read(struct vmctx *ctx, int vcpu, struct vga *vga,
200 uint64_t offset, int size);
A Dvhost.h62 uint64_t vhost_features;
68 uint64_t vhost_ext_features;
98 int vq_idx, uint64_t vhost_features,
99 uint64_t vhost_ext_features, uint32_t busyloop_timeout);
A Dmem.h36 typedef int (*mem_func_t)(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
37 int size, uint64_t *val, void *arg1, long arg2);
45 uint64_t base;
46 uint64_t size;
A Dsw_load.h50 uint64_t baseaddr;
52 uint64_t length;
75 int add_e820_entry(struct e820_entry *e820, int len, uint64_t start,
76 uint64_t size, uint32_t type);
A Dvbs_common_if.h21 uint64_t msix_addr;
37 uint64_t pio_range_start;
38 uint64_t pio_range_len; /* PIO bar address initialized by guest OS */
A Dsbuf.h19 static inline void sbuf_clear_flags(struct shared_buf *sbuf, uint64_t flags) in sbuf_clear_flags()
24 static inline void sbuf_set_flags(struct shared_buf *sbuf, uint64_t flags) in sbuf_set_flags()
29 static inline void sbuf_add_flags(struct shared_buf *sbuf, uint64_t flags) in sbuf_add_flags()
A Dvssram.h45 uint64_t base;
50 uint64_t get_vssram_gpa_base(void);
51 uint64_t get_vssram_size(void);
/devicemodel/core/
A Dmem.c49 uint64_t mr_base;
50 uint64_t mr_end;
76 mmio_rb_lookup(struct mmio_rb_tree *rbt, uint64_t addr, in mmio_rb_lookup()
131 mem_read(void *ctx, int vcpu, uint64_t gpa, uint64_t *rval, int size, void *arg) in mem_read()
142 mem_write(void *ctx, int vcpu, uint64_t gpa, uint64_t wval, int size, void *arg) in mem_write()
155 uint64_t paddr = mmio_req->address; in emulate_mem()
183 err = mem_read(ctx, 0, paddr, (uint64_t *)&mmio_req->value, in emulate_mem()
A Dsw_load_vsbl.c90 uint64_t e820_table_address;
91 uint64_t e820_entries;
92 uint64_t acpi_table_address;
93 uint64_t acpi_table_size;
94 uint64_t guest_part_info_address;
95 uint64_t guest_part_info_size;
96 uint64_t vsbl_address;
97 uint64_t vsbl_size;
98 uint64_t bootargs_address;
/devicemodel/hw/platform/tpm/
A Dtpm_crb.c144 uint64_t ctrl_rsp_addr;
161 static uint64_t mmio_read(void *addr, int size) in mmio_read()
163 uint64_t val = 0; in mmio_read()
175 val = *(uint64_t *)addr; in mmio_read()
196 *(uint64_t *)addr = val; in mmio_write()
203 static uint64_t crb_reg_read(struct tpm_crb_vdev *tpm_vdev, uint64_t addr, int size) in crb_reg_read()
206 uint64_t off; in crb_reg_read()
289 static void crb_reg_write(struct tpm_crb_vdev *tpm_vdev, uint64_t addr, int size, uint64_t val) in crb_reg_write()
293 uint64_t off = addr - get_vtpm_crb_mmio_addr(); in crb_reg_write()
367 int size, uint64_t *val, void *arg1, long arg2) in tpm_crb_reg_handler()
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/devicemodel/hw/platform/
A Dhpet.c151 const uint64_t
154 static uint64_t cap = 0; in vhpet_capabilities()
340 uint64_t newexp; in vhpet_timer_handler()
411 uint64_t delta_ticks; in vhpet_adjust_compval()
586 update_register(uint64_t *const regptr, const uint64_t data, in update_register()
587 const uint64_t mask) in update_register()
595 uint64_t mask) in vhpet_timer_update_config()
692 vhpet_mmio_write(struct vhpet *vhpet, int vcpuid, uint64_t gpa, uint64_t *wval, in vhpet_mmio_write()
845 vhpet_mmio_read(struct vhpet *vhpet, int vcpuid, uint64_t gpa, uint64_t *rval, in vhpet_mmio_read()
849 uint64_t data = 0; in vhpet_mmio_read()
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/devicemodel/hw/platform/vssram/
A Dvssram.c37 ((uint64_t)e - (uint64_t)rtct) < rtct->length; \
50 uint64_t vcpumask;
59 uint64_t vma_base;
60 uint64_t gpa_base;
72 static uint64_t guest_pcpumask;
78 static uint64_t vssram_size;
79 static uint64_t vssram_gpa_base;
862 uint64_t gpa = gpa_start; in vssram_merge_l2l3_gpa_regions()
890 uint64_t gpa, gpa_size; in vssram_config_buffers_gpa()
1067 uint64_t inclusive_size; in vrtct_add_ssram_entries()
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/devicemodel/hw/pci/
A Divshmem.c91 uint64_t bar_addr; in create_ivshmem_from_dm()
120 bar_addr |= ((uint64_t)pci_get_cfgdata32(vdev, PCIR_BAR(IVSHMEM_MEM_BAR + 1)) << 32); in create_ivshmem_from_dm()
123 (uint64_t)addr, bar_addr, size); in create_ivshmem_from_dm()
125 (uint64_t)addr, PROT_RW) < 0) { in create_ivshmem_from_dm()
152 uint64_t addr = 0; in create_ivshmem_from_hv()
176 int baridx, uint64_t offset, int size, uint64_t value) in pci_ivshmem_write()
202 uint64_t
204 int baridx, uint64_t offset, int size) in pci_ivshmem_read()
206 uint64_t val = ~0; in pci_ivshmem_read()
A Dcore.c166 is_io_rgns_overlap(uint64_t x1, uint64_t x2, uint64_t y1, uint64_t y2) in is_io_rgns_overlap()
180 adjust_bar_region(uint64_t *base, uint64_t size, int bar_type) in adjust_bar_region()
424 uint64_t
488 uint64_t mask; in bar_value()
502 uint64_t offset; in pci_emul_io_handler()
529 uint64_t offset; in pci_emul_mem_handler()
572 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, in pci_emul_alloc_resource()
575 uint64_t base; in pci_emul_alloc_resource()
603 uint64_t size) in pci_emul_alloc_bar()
2608 uint64_t offset, int size, uint64_t value) in pci_emul_diow()
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A Dnpk.c149 static uint64_t sw_bar_base;
152 static inline uint32_t *offset2reg(uint64_t offset) in offset2reg()
336 int baridx, uint64_t offset, int size, uint64_t value) in pci_npk_write()
351 static uint64_t pci_npk_read(struct vmctx *ctx, int vcpu, struct pci_vdev *dev, in pci_npk_read()
352 int baridx, uint64_t offset, int size) in pci_npk_read()
359 return (uint64_t)val; in pci_npk_read()
366 return (uint64_t)val; in pci_npk_read()
/devicemodel/hw/pci/virtio/
A Dvirtio_hyper_dmabuf.c65 uint64_t pio_start, uint64_t pio_len);
70 uint64_t msix_addr, uint32_t msix_data);
73 static void virtio_hyper_dmabuf_set_status(void *, uint64_t);
113 uint32_t feature, uint64_t pio_start, in virtio_hyper_dmabuf_k_dev_set()
114 uint64_t pio_len) in virtio_hyper_dmabuf_k_dev_set()
131 uint16_t msix_idx, uint64_t msix_addr, in virtio_hyper_dmabuf_k_vq_set()
203 virtio_hyper_dmabuf_set_status(void *base, uint64_t status) in virtio_hyper_dmabuf_set_status()
208 uint64_t msix_addr = 0; in virtio_hyper_dmabuf_set_status()
A Dvirtio.c390 uint64_t phys; in virtio_vq_init()
442 uint64_t phys; in virtio_vq_enable()
894 static uint64_t
1036 int baridx, uint64_t offset, int size, uint64_t value) in virtio_pci_legacy_write()
1498 uint64_t value) in virtio_common_cfg_write()
1653 uint64_t max; in virtio_device_cfg_read()
1686 uint64_t max; in virtio_device_cfg_write()
1719 uint64_t idx; in virtio_notify_cfg_write()
1868 uint64_t idx; in virtio_pci_modern_pio_write()
1921 uint64_t
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A Dvirtio_audio.c69 uint32_t feature, uint64_t pio_start,
70 uint64_t pio_len);
74 uint16_t msix_idx, uint64_t msix_addr,
78 static void virtio_audio_k_set_status(void *base, uint64_t status);
119 uint64_t pio_start, in virtio_audio_kernel_dev_set()
120 uint64_t pio_len) in virtio_audio_kernel_dev_set()
137 uint32_t pfn, uint16_t msix_idx, uint64_t msix_addr, in virtio_audio_kernel_vq_set()
215 virtio_audio_k_set_status(void *base, uint64_t status) in virtio_audio_k_set_status()
220 uint64_t msix_addr = 0; in virtio_audio_k_set_status()
A Dvirtio_ipu.c71 uint64_t pio_start, uint64_t pio_len);
76 uint16_t msix_idx, uint64_t msix_addr,
80 static void virtio_ipu_set_status(void *, uint64_t);
122 uint32_t feature, uint64_t pio_start, in virtio_ipu_k_dev_set()
123 uint64_t pio_len) in virtio_ipu_k_dev_set()
140 uint16_t msix_idx, uint64_t msix_addr, in virtio_ipu_k_vq_set()
222 virtio_ipu_set_status(void *base, uint64_t status) in virtio_ipu_set_status()
228 uint64_t msix_addr = 0; in virtio_ipu_set_status()

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