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Searched refs:val (Results 1 – 25 of 36) sorted by relevance

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/devicemodel/include/
A Datomic.h20 #define atomic_store(ptr, val) \ argument
23 #define atomic_xchg(ptr, val) \ argument
88 __sync_add_and_fetch(ptr, val)
90 __sync_sub_and_fetch(ptr, val)
92 __sync_and_and_fetch(ptr, val)
94 __sync_xor_and_fetch(ptr, val)
96 __sync_or_and_fetch(ptr, val)
101 __sync_fetch_and_add(ptr, val)
103 __sync_fetch_and_sub(ptr, val)
105 __sync_fetch_and_and(ptr, val)
[all …]
A Drpmb_sim.h30 static inline uint32_t swap32(uint32_t val) in swap32() argument
32 return ((val & (uint32_t)0x000000ffUL) << 24) in swap32()
33 | ((val & (uint32_t)0x0000ff00UL) << 8) in swap32()
34 | ((val & (uint32_t)0x00ff0000UL) >> 8) in swap32()
35 | ((val & (uint32_t)0xff000000UL) >> 24); in swap32()
38 static inline uint16_t swap16(uint16_t val) in swap16() argument
40 return ((val & (uint16_t)0x00ffU) << 8) in swap16()
41 | ((val & (uint16_t)0xff00U) >> 8); in swap16()
A Ddm_string.h23 int dm_strtol(const char *s, char **end, unsigned int base, long *val);
37 int dm_strtoi(const char *s, char **end, unsigned int base, int *val);
51 int dm_strtoul(const char *s, char **end, unsigned int base, unsigned long *val);
65 int dm_strtoui(const char *s, char **end, unsigned int base, unsigned int *val);
A Dpci_core.h81 int bytes, uint32_t val);
313 int bytes, uint32_t val);
315 int bytes, uint32_t val);
413 pci_set_cfgdata8(struct pci_vdev *dev, int offset, uint8_t val) in pci_set_cfgdata8() argument
419 *(uint8_t *)(dev->cfgdata + offset) = val; in pci_set_cfgdata8()
430 pci_set_cfgdata16(struct pci_vdev *dev, int offset, uint16_t val) in pci_set_cfgdata16() argument
436 *(uint16_t *)(dev->cfgdata + offset) = val; in pci_set_cfgdata16()
447 pci_set_cfgdata32(struct pci_vdev *dev, int offset, uint32_t val) in pci_set_cfgdata32() argument
453 *(uint32_t *)(dev->cfgdata + offset) = val; in pci_set_cfgdata32()
A Dps2kbd.h37 int ps2kbd_read(struct ps2kbd_info *kbd, uint8_t *val);
38 void ps2kbd_write(struct ps2kbd_info *kbd, uint8_t val);
A Dps2mouse.h37 int ps2mouse_read(struct ps2mouse_info *mouse, uint8_t *val);
38 void ps2mouse_write(struct ps2mouse_info *mouse, uint8_t val, int insert);
A Diodev.h39 u_int val; member
A Dvga.h190 uint8_t *val, void *arg);
192 uint8_t val, void *arg);
A Dirq.h44 void pirq_write(struct vmctx *ctx, int pin, uint8_t val);
/devicemodel/hw/
A Dvga.c473 val = (val >> vd->vga_gc.gc_rotate) | in vga_mem_wr_handler()
591 val = (val >> vd->vga_gc.gc_rotate) | in vga_mem_wr_handler()
824 *val = 0xFF; in vga_port_in_handler()
853 *val = 0xFF; in vga_port_in_handler()
946 *val = 0; in vga_port_in_handler()
949 *val = 0; in vga_port_in_handler()
952 *val = 0xFF; in vga_port_in_handler()
1239 uint8_t val; in vga_port_handler() local
1371 uint8_t val; in vga_ioport_write() local
1392 uint8_t val; in vga_ioport_read() local
[all …]
/devicemodel/lib/
A Ddm_string.c15 dm_strtol(const char *s, char **end, unsigned int base, long *val) in dm_strtol() argument
20 *val = strtol(s, end, base); in dm_strtol()
27 dm_strtoi(const char *s, char **end, unsigned int base, int *val) in dm_strtoi() argument
35 *val = (int)l_val; in dm_strtoi()
40 dm_strtoul(const char *s, char **end, unsigned int base, unsigned long *val) in dm_strtoul() argument
45 *val = strtoul(s, end, base); in dm_strtoul()
52 dm_strtoui(const char *s, char **end, unsigned int base, unsigned int *val) in dm_strtoui() argument
60 *val = (unsigned int)l_val; in dm_strtoui()
/devicemodel/hw/platform/tpm/
A Dtpm_crb.c163 uint64_t val = 0; in mmio_read() local
166 val = *(uint8_t *)addr; in mmio_read()
169 val = *(uint16_t *)addr; in mmio_read()
172 val = *(uint32_t *)addr; in mmio_read()
175 val = *(uint64_t *)addr; in mmio_read()
180 return val; in mmio_read()
187 *(uint8_t *)addr = val; in mmio_write()
190 *(uint16_t *)addr = val; in mmio_write()
205 uint32_t val; in crb_reg_read() local
216 return val; in crb_reg_read()
[all …]
/devicemodel/hw/pci/
A Duart.c79 uint8_t val = 0xff; in pci_uart_read() local
82 val = uart_read(dev->arg, offset); in pci_uart_read()
83 return val; in pci_uart_read()
89 char *tmp, *val = NULL; in pci_uart_init() local
96 tmp = val= strdup(opts); in pci_uart_init()
101 tmp = strsep(&val, ":"); in pci_uart_init()
102 if (!val) { in pci_uart_init()
105 if (dm_strtoui(val, &val, 10, &vuart_idx)) { in pci_uart_init()
A Dcore.c493 return val & mask; in bar_value()
564 *val = bar_value(size, *val); in pci_emul_mem_handler()
1122 uint32_t val = 0; in pci_is_msi_masked() local
1146 uint32_t val; in pci_set_msi_pending() local
1150 &val, false); in pci_set_msi_pending()
1157 val = (1 << index) | val; in pci_set_msi_pending()
1159 val = (~(1 << index)) & val; in pci_set_msi_pending()
1296 val = msgctrl; in msixcap_cfgwrite()
1323 val = msgctrl; in msicap_cfgwrite()
1419 val >>= 16; in pci_emul_capwrite()
[all …]
A Dwdt_i6300esb.c54 #define TIMER_TO_SECONDS(val) (val >> 10) argument
220 int offset, int bytes, uint32_t val) in pci_wdt_cfg_write() argument
226 __func__, offset, bytes, val); in pci_wdt_cfg_write()
229 wdt_state.reboot_enabled = ((val & ESB_WDT_REBOOT) == 0); in pci_wdt_cfg_write()
230 wdt_state.intr_enabled = ((val & ESB_WDT_INT_MSK) == 0); in pci_wdt_cfg_write()
235 wdt_state.locked = ((val & ESB_WDT_LOCK) != 0); in pci_wdt_cfg_write()
237 wdt_state.wdt_enabled = ((val & ESB_WDT_ENABLE) != 0); in pci_wdt_cfg_write()
A Divshmem.c206 uint64_t val = ~0; in pci_ivshmem_read() local
219 val = 0; in pci_ivshmem_read()
226 val = 0; in pci_ivshmem_read()
237 val &= 0xFF; in pci_ivshmem_read()
240 val &= 0xFFFF; in pci_ivshmem_read()
243 val &= 0xFFFFFFFF; in pci_ivshmem_read()
247 return val; in pci_ivshmem_read()
A Dnpk.c354 uint32_t *reg, val = 0; in pci_npk_read() local
356 DPRINTF(("R %d +0x%lx[%d] val 0x%x\n", baridx, offset, size, val)); in pci_npk_read()
359 return (uint64_t)val; in pci_npk_read()
364 val = *reg; in pci_npk_read()
366 return (uint64_t)val; in pci_npk_read()
A Dirq.c89 pirq_write(struct vmctx *ctx, int pin, uint8_t val) in pirq_write() argument
98 if (pirq->reg != (val & (PIRQ_DIS | PIRQ_IRQ))) { in pirq_write()
101 pirq->reg = val & (PIRQ_DIS | PIRQ_IRQ); in pirq_write()
A Dpassthrough.c153 uint32_t val; in passthru_set_power_state() local
157 val = read_config(ptdev->phys_dev, in passthru_set_power_state()
159 val = (val & ~PCIM_PSTAT_DMASK) | dpsts; in passthru_set_power_state()
162 ptdev->pmcap.capoff + PCIR_POWER_STATUS, 2, val); in passthru_set_power_state()
1077 int coff, int bytes, uint32_t val) in passthru_cfgwrite() argument
1084 if ((val & PCIM_BIOS_ADDR_MASK) == PCIM_BIOS_ADDR_MASK) { in passthru_cfgwrite()
1091 } else if (val == 0) { in passthru_cfgwrite()
1093 pci_set_cfgdata32(dev, PCIR_BIOS, val); in passthru_cfgwrite()
1101 val, dev->bus, dev->slot, dev->func); in passthru_cfgwrite()
1105 write_config(ptdev->phys_dev, coff, bytes, val); in passthru_cfgwrite()
/devicemodel/hw/platform/
A Dps2mouse.c130 fifo->buf[fifo->windex] = val; in fifo_put()
143 *val = fifo->buf[fifo->rindex]; in fifo_get()
237 retval = fifo_get(mouse, val); in ps2mouse_read()
272 mouse->sampling_rate = val; in ps2mouse_write()
276 mouse->resolution = val; in ps2mouse_write()
281 "command byte 0x%02x\n", val); in ps2mouse_write()
287 fifo_put(mouse, val); in ps2mouse_write()
289 switch (val) { in ps2mouse_write()
314 mouse->curcmd = val; in ps2mouse_write()
340 mouse->curcmd = val; in ps2mouse_write()
[all …]
A Dps2kbd.c92 fifo_put(struct ps2kbd_info *kbd, uint8_t val) in fifo_put() argument
98 fifo->buf[fifo->windex] = val; in fifo_put()
105 fifo_get(struct ps2kbd_info *kbd, uint8_t *val) in fifo_get() argument
111 *val = fifo->buf[fifo->rindex]; in fifo_get()
126 retval = fifo_get(kbd, val); in ps2kbd_read()
149 "command byte 0x%02x\n", val); in ps2kbd_write()
154 switch (val) { in ps2kbd_write()
173 kbd->curcmd = val; in ps2kbd_write()
182 kbd->curcmd = val; in ps2kbd_write()
189 kbd->curcmd = val; in ps2kbd_write()
[all …]
A Dpit.c174 uint32_t val; in pit_cr_val() local
176 val = cr[0] | (uint16_t)cr[1] << 8; in pit_cr_val()
179 if (val == 0) { in pit_cr_val()
180 val = 0x10000; in pit_cr_val()
183 return val; in pit_cr_val()
462 sel = val & TIMER_SEL_MASK; in vpit_update_mode()
463 rw = val & TIMER_RW_MASK; in vpit_update_mode()
464 mode = val & TIMER_MODE_MASK; in vpit_update_mode()
467 return pit_readback(vpit, val); in vpit_update_mode()
519 uint8_t val; in vpit_handler() local
[all …]
A Datkbdc.c66 atkbdc_kbd_queue_data(struct atkbdc_base *base, uint8_t val) in atkbdc_kbd_queue_data() argument
69 base->kbd.buffer[base->kbd.bwr] = val; in atkbdc_kbd_queue_data()
118 uint8_t val; in atkbdc_kbd_read() local
122 while (ps2kbd_read(base->ps2kbd, &val) != -1) { in atkbdc_kbd_read()
123 if (val == 0xf0) { in atkbdc_kbd_read()
127 val = translation[val] | release; in atkbdc_kbd_read()
129 atkbdc_kbd_queue_data(base, val); in atkbdc_kbd_read()
134 if (ps2kbd_read(base->ps2kbd, &val) != -1) in atkbdc_kbd_read()
135 atkbdc_kbd_queue_data(base, val); in atkbdc_kbd_read()
/devicemodel/core/
A Dvm_event.c192 cJSON *val; in generate_vm_event_message() local
198 val = cJSON_CreateNumber(event->type); in generate_vm_event_message()
199 if (val == NULL) in generate_vm_event_message()
201 cJSON_AddItemToObject(event_obj, "vm_event", val); in generate_vm_event_message()
236 cJSON *val; in gen_rtc_chg_jdata() local
238 val = cJSON_CreateNumber(data->delta_time); in gen_rtc_chg_jdata()
239 if (val != NULL) { in gen_rtc_chg_jdata()
242 val = cJSON_CreateNumber(data->last_time); in gen_rtc_chg_jdata()
243 if (val != NULL) { in gen_rtc_chg_jdata()
310 eventfd_t val; in vm_event_thread() local
[all …]
/devicemodel/core/cmd_monitor/
A Dcommand_handler.c30 cJSON *val; in generate_ack_message() local
35 val = cJSON_CreateNumber(ret_val); in generate_ack_message()
36 if (val == NULL) in generate_ack_message()
38 cJSON_AddItemToObject(ret_obj, "ack", val); in generate_ack_message()
47 int ret = 0, val; in send_socket_ack() local
54 val = normal ? SUCCEEDED : FAILED; in send_socket_ack()
55 ack_message = generate_ack_message(val); in send_socket_ack()

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