1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MSR_H 8 #define MSR_H 9 10 /* architectural (common) MSRs */ 11 12 /* Machine check address for MC exception handler */ 13 #define MSR_IA32_P5_MC_ADDR 0x00000000U 14 /* Machine check error type for MC exception handler */ 15 #define MSR_IA32_P5_MC_TYPE 0x00000001U 16 /* System coherence line size for MWAIT/MONITOR */ 17 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006U 18 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010U 19 #define MSR_IA32_PLATFORM_ID 0x00000017U 20 #define MSR_IA32_APIC_BASE 0x0000001BU 21 #define MSR_TEST_CTL 0x00000033U 22 #define MSR_IA32_FEATURE_CONTROL 0x0000003AU 23 #define MSR_IA32_TSC_ADJUST 0x0000003BU 24 /* Speculation Control */ 25 #define MSR_IA32_SPEC_CTRL 0x00000048U 26 /* Prediction Command */ 27 #define MSR_IA32_PRED_CMD 0x00000049U 28 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079U 29 #define MSR_IA32_BIOS_SIGN_ID 0x0000008BU 30 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008CU 31 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008DU 32 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008EU 33 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008FU 34 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009BU 35 #define MSR_IA32_SMBASE 0x0000009EU 36 #define MSR_IA32_PMC0 0x000000C1U 37 #define MSR_IA32_PMC1 0x000000C2U 38 #define MSR_IA32_PMC2 0x000000C3U 39 #define MSR_IA32_PMC3 0x000000C4U 40 #define MSR_IA32_PMC4 0x000000C5U 41 #define MSR_IA32_PMC5 0x000000C6U 42 #define MSR_IA32_PMC6 0x000000C7U 43 #define MSR_IA32_PMC7 0x000000C8U 44 #define MSR_IA32_CORE_CAPABILITIES 0x000000CFU 45 #define MSR_IA32_UMWAIT_CONTROL 0x000000E1U 46 /* Max. qualified performance clock counter */ 47 #define MSR_IA32_MPERF 0x000000E7U 48 /* Actual performance clock counter */ 49 #define MSR_IA32_APERF 0x000000E8U 50 #define MSR_IA32_MTRR_CAP 0x000000FEU 51 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010AU 52 #define MSR_IA32_FLUSH_CMD 0x0000010BU 53 #define MSR_MISC_FEATURE_ENABLES 0x00000140U 54 #define MSR_IA32_SYSENTER_CS 0x00000174U 55 #define MSR_IA32_SYSENTER_ESP 0x00000175U 56 #define MSR_IA32_SYSENTER_EIP 0x00000176U 57 #define MSR_IA32_MCG_CAP 0x00000179U 58 #define MSR_IA32_MCG_STATUS 0x0000017AU 59 #define MSR_IA32_MCG_CTL 0x0000017BU 60 #define MSR_IA32_PERFEVTSEL0 0x00000186U 61 #define MSR_IA32_PERFEVTSEL1 0x00000187U 62 #define MSR_IA32_PERFEVTSEL2 0x00000188U 63 #define MSR_IA32_PERFEVTSEL3 0x00000189U 64 #define MSR_IA32_PERF_STATUS 0x00000198U 65 #define MSR_IA32_PERF_CTL 0x00000199U 66 #define MSR_IA32_CLOCK_MODULATION 0x0000019AU 67 #define MSR_IA32_THERM_INTERRUPT 0x0000019BU 68 #define MSR_IA32_THERM_STATUS 0x0000019CU 69 #define MSR_IA32_MISC_ENABLE 0x000001A0U 70 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0U 71 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1U 72 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2U 73 #define MSR_IA32_DEBUGCTL 0x000001D9U 74 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2U 75 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3U 76 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8U 77 #define MSR_IA32_CPU_DCA_CAP 0x000001F9U 78 #define MSR_IA32_DCA_0_CAP 0x000001FAU 79 #define MSR_IA32_MTRR_PHYSBASE_0 0x00000200U 80 #define MSR_IA32_MTRR_PHYSMASK_0 0x00000201U 81 #define MSR_IA32_MTRR_PHYSBASE_1 0x00000202U 82 #define MSR_IA32_MTRR_PHYSMASK_1 0x00000203U 83 #define MSR_IA32_MTRR_PHYSBASE_2 0x00000204U 84 #define MSR_IA32_MTRR_PHYSMASK_2 0x00000205U 85 #define MSR_IA32_MTRR_PHYSBASE_3 0x00000206U 86 #define MSR_IA32_MTRR_PHYSMASK_3 0x00000207U 87 #define MSR_IA32_MTRR_PHYSBASE_4 0x00000208U 88 #define MSR_IA32_MTRR_PHYSMASK_4 0x00000209U 89 #define MSR_IA32_MTRR_PHYSBASE_5 0x0000020AU 90 #define MSR_IA32_MTRR_PHYSMASK_5 0x0000020BU 91 #define MSR_IA32_MTRR_PHYSBASE_6 0x0000020CU 92 #define MSR_IA32_MTRR_PHYSMASK_6 0x0000020DU 93 #define MSR_IA32_MTRR_PHYSBASE_7 0x0000020EU 94 #define MSR_IA32_MTRR_PHYSMASK_7 0x0000020FU 95 #define MSR_IA32_MTRR_PHYSBASE_8 0x00000210U 96 #define MSR_IA32_MTRR_PHYSMASK_8 0x00000211U 97 #define MSR_IA32_MTRR_PHYSBASE_9 0x00000212U 98 #define MSR_IA32_MTRR_PHYSMASK_9 0x00000213U 99 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250U 100 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258U 101 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259U 102 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268U 103 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269U 104 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026AU 105 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026BU 106 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026CU 107 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026DU 108 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026EU 109 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026FU 110 #define MSR_IA32_PAT 0x00000277U 111 #define MSR_IA32_MC0_CTL2 0x00000280U 112 #define MSR_IA32_MC1_CTL2 0x00000281U 113 #define MSR_IA32_MC2_CTL2 0x00000282U 114 #define MSR_IA32_MC3_CTL2 0x00000283U 115 #define MSR_IA32_MC4_CTL2 0x00000284U 116 #define MSR_IA32_MC5_CTL2 0x00000285U 117 #define MSR_IA32_MC6_CTL2 0x00000286U 118 #define MSR_IA32_MC7_CTL2 0x00000287U 119 #define MSR_IA32_MC8_CTL2 0x00000288U 120 #define MSR_IA32_MC9_CTL2 0x00000289U 121 #define MSR_IA32_MC10_CTL2 0x0000028AU 122 #define MSR_IA32_MC11_CTL2 0x0000028BU 123 #define MSR_IA32_MC12_CTL2 0x0000028CU 124 #define MSR_IA32_MC13_CTL2 0x0000028DU 125 #define MSR_IA32_MC14_CTL2 0x0000028EU 126 #define MSR_IA32_MC15_CTL2 0x0000028FU 127 #define MSR_IA32_MC16_CTL2 0x00000290U 128 #define MSR_IA32_MC17_CTL2 0x00000291U 129 #define MSR_IA32_MC18_CTL2 0x00000292U 130 #define MSR_IA32_MC19_CTL2 0x00000293U 131 #define MSR_IA32_MC20_CTL2 0x00000294U 132 #define MSR_IA32_MC21_CTL2 0x00000295U 133 #define MSR_IA32_MC31_CTL2 0x0000029FU 134 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FFU 135 #define MSR_SGXOWNEREPOCH0 0x00000300U 136 #define MSR_SGXOWNEREPOCH1 0x00000301U 137 #define MSR_IA32_FIXED_CTR0 0x00000309U 138 #define MSR_IA32_FIXED_CTR1 0x0000030AU 139 #define MSR_IA32_FIXED_CTR2 0x0000030BU 140 #define MSR_IA32_PERF_CAPABILITIES 0x00000345U 141 #define MSR_IA32_FIXED_CTR_CTL 0x0000038DU 142 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038EU 143 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038FU 144 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390U 145 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391U 146 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392U 147 #define MSR_IA32_PEBS_ENABLE 0x000003F1U 148 #define MSR_IA32_MC0_CTL 0x00000400U 149 #define MSR_IA32_MC0_STATUS 0x00000401U 150 #define MSR_IA32_MC0_ADDR 0x00000402U 151 #define MSR_IA32_MC0_MISC 0x00000403U 152 #define MSR_IA32_MC1_CTL 0x00000404U 153 #define MSR_IA32_MC1_STATUS 0x00000405U 154 #define MSR_IA32_MC1_ADDR 0x00000406U 155 #define MSR_IA32_MC1_MISC 0x00000407U 156 #define MSR_IA32_MC2_CTL 0x00000408U 157 #define MSR_IA32_MC2_STATUS 0x00000409U 158 #define MSR_IA32_MC2_ADDR 0x0000040AU 159 #define MSR_IA32_MC2_MISC 0x0000040BU 160 #define MSR_IA32_MC3_CTL 0x0000040CU 161 #define MSR_IA32_MC3_STATUS 0x0000040DU 162 #define MSR_IA32_MC3_ADDR 0x0000040EU 163 #define MSR_IA32_MC3_MISC 0x0000040FU 164 #define MSR_IA32_MC4_CTL 0x00000410U 165 #define MSR_IA32_MC4_STATUS 0x00000411U 166 #define MSR_IA32_MC4_ADDR 0x00000412U 167 #define MSR_IA32_MC4_MISC 0x00000413U 168 #define MSR_IA32_MC5_CTL 0x00000414U 169 #define MSR_IA32_MC5_STATUS 0x00000415U 170 #define MSR_IA32_MC5_ADDR 0x00000416U 171 #define MSR_IA32_MC5_MISC 0x00000417U 172 #define MSR_IA32_MC6_CTL 0x00000418U 173 #define MSR_IA32_MC6_STATUS 0x00000419U 174 #define MSR_IA32_MC6_ADDR 0x0000041AU 175 #define MSR_IA32_MC6_MISC 0x0000041BU 176 #define MSR_IA32_MC7_CTL 0x0000041CU 177 #define MSR_IA32_MC7_STATUS 0x0000041DU 178 #define MSR_IA32_MC7_ADDR 0x0000041EU 179 #define MSR_IA32_MC7_MISC 0x0000041FU 180 #define MSR_IA32_MC8_CTL 0x00000420U 181 #define MSR_IA32_MC8_STATUS 0x00000421U 182 #define MSR_IA32_MC8_ADDR 0x00000422U 183 #define MSR_IA32_MC8_MISC 0x00000423U 184 #define MSR_IA32_MC9_CTL 0x00000424U 185 #define MSR_IA32_MC9_STATUS 0x00000425U 186 #define MSR_IA32_MC9_ADDR 0x00000426U 187 #define MSR_IA32_MC9_MISC 0x00000427U 188 #define MSR_IA32_MC10_CTL 0x00000428U 189 #define MSR_IA32_MC10_STATUS 0x00000429U 190 #define MSR_IA32_MC10_ADDR 0x0000042AU 191 #define MSR_IA32_MC10_MISC 0x0000042BU 192 #define MSR_IA32_MC11_CTL 0x0000042CU 193 #define MSR_IA32_MC11_STATUS 0x0000042DU 194 #define MSR_IA32_MC11_ADDR 0x0000042EU 195 #define MSR_IA32_MC11_MISC 0x0000042FU 196 #define MSR_IA32_MC12_CTL 0x00000430U 197 #define MSR_IA32_MC12_STATUS 0x00000431U 198 #define MSR_IA32_MC12_ADDR 0x00000432U 199 #define MSR_IA32_MC12_MISC 0x00000433U 200 #define MSR_IA32_MC13_CTL 0x00000434U 201 #define MSR_IA32_MC13_STATUS 0x00000435U 202 #define MSR_IA32_MC13_ADDR 0x00000436U 203 #define MSR_IA32_MC13_MISC 0x00000437U 204 #define MSR_IA32_MC14_CTL 0x00000438U 205 #define MSR_IA32_MC14_STATUS 0x00000439U 206 #define MSR_IA32_MC14_ADDR 0x0000043AU 207 #define MSR_IA32_MC14_MISC 0x0000043BU 208 #define MSR_IA32_MC15_CTL 0x0000043CU 209 #define MSR_IA32_MC15_STATUS 0x0000043DU 210 #define MSR_IA32_MC15_ADDR 0x0000043EU 211 #define MSR_IA32_MC15_MISC 0x0000043FU 212 #define MSR_IA32_MC16_CTL 0x00000440U 213 #define MSR_IA32_MC16_STATUS 0x00000441U 214 #define MSR_IA32_MC16_ADDR 0x00000442U 215 #define MSR_IA32_MC16_MISC 0x00000443U 216 #define MSR_IA32_MC17_CTL 0x00000444U 217 #define MSR_IA32_MC17_STATUS 0x00000445U 218 #define MSR_IA32_MC17_ADDR 0x00000446U 219 #define MSR_IA32_MC17_MISC 0x00000447U 220 #define MSR_IA32_MC18_CTL 0x00000448U 221 #define MSR_IA32_MC18_STATUS 0x00000449U 222 #define MSR_IA32_MC18_ADDR 0x0000044AU 223 #define MSR_IA32_MC18_MISC 0x0000044BU 224 #define MSR_IA32_MC19_CTL 0x0000044CU 225 #define MSR_IA32_MC19_STATUS 0x0000044DU 226 #define MSR_IA32_MC19_ADDR 0x0000044EU 227 #define MSR_IA32_MC19_MISC 0x0000044FU 228 #define MSR_IA32_MC20_CTL 0x00000450U 229 #define MSR_IA32_MC20_STATUS 0x00000451U 230 #define MSR_IA32_MC20_ADDR 0x00000452U 231 #define MSR_IA32_MC20_MISC 0x00000453U 232 #define MSR_IA32_MC21_CTL 0x00000454U 233 #define MSR_IA32_MC21_STATUS 0x00000455U 234 #define MSR_IA32_MC21_ADDR 0x00000456U 235 #define MSR_IA32_MC21_MISC 0x00000457U 236 #define MSR_IA32_MC28_CTL 0x00000470U 237 #define MSR_IA32_MC28_STATUS 0x00000471U 238 #define MSR_IA32_MC28_ADDR 0x00000472U 239 #define MSR_IA32_MC28_MISC 0x00000473U 240 #define MSR_IA32_VMX_BASIC 0x00000480U 241 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481U 242 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482U 243 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483U 244 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484U 245 #define MSR_IA32_VMX_MISC 0x00000485U 246 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486U 247 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487U 248 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488U 249 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489U 250 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048AU 251 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048BU 252 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048CU 253 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048DU 254 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048EU 255 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048FU 256 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490U 257 #define MSR_IA32_VMX_VMFUNC 0x00000491U 258 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492U 259 #define MSR_IA32_A_PMC0 0x000004C1U 260 #define MSR_IA32_A_PMC1 0x000004C2U 261 #define MSR_IA32_A_PMC2 0x000004C3U 262 #define MSR_IA32_A_PMC3 0x000004C4U 263 #define MSR_IA32_A_PMC4 0x000004C5U 264 #define MSR_IA32_A_PMC5 0x000004C6U 265 #define MSR_IA32_A_PMC6 0x000004C7U 266 #define MSR_IA32_A_PMC7 0x000004C8U 267 #define MSR_IA32_MCG_EXT_CTL 0x000004D0U 268 #define MSR_IA32_SGX_SVN_STATUS 0x00000500U 269 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560U 270 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561U 271 #define MSR_IA32_RTIT_CTL 0x00000570U 272 #define MSR_IA32_RTIT_STATUS 0x00000571U 273 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572U 274 #define MSR_IA32_RTIT_ADDR0_A 0x00000580U 275 #define MSR_IA32_RTIT_ADDR0_B 0x00000581U 276 #define MSR_IA32_RTIT_ADDR1_A 0x00000582U 277 #define MSR_IA32_RTIT_ADDR1_B 0x00000583U 278 #define MSR_IA32_RTIT_ADDR2_A 0x00000584U 279 #define MSR_IA32_RTIT_ADDR2_B 0x00000585U 280 #define MSR_IA32_RTIT_ADDR3_A 0x00000586U 281 #define MSR_IA32_RTIT_ADDR3_B 0x00000587U 282 #define MSR_IA32_DS_AREA 0x00000600U 283 #define MSR_IA32_U_CET 0x000006A0U 284 #define MSR_IA32_S_CET 0x000006A2U 285 #define MSR_IA32_PL0_SSP 0x000006A4U 286 #define MSR_IA32_PL1_SSP 0x000006A5U 287 #define MSR_IA32_PL2_SSP 0x000006A6U 288 #define MSR_IA32_PL3_SSP 0x000006A7U 289 #define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR 0x000006A8U 290 #define MSR_IA32_TSC_DEADLINE 0x000006E0U 291 #define MSR_IA32_PM_ENABLE 0x00000770U 292 #define MSR_IA32_HWP_CAPABILITIES 0x00000771U 293 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772U 294 #define MSR_IA32_HWP_INTERRUPT 0x00000773U 295 #define MSR_IA32_HWP_REQUEST 0x00000774U 296 #define MSR_IA32_HWP_PECI_REQUEST_INFO 0x00000775U 297 #define MSR_IA32_HWP_CTL 0x00000776U 298 #define MSR_IA32_HWP_STATUS 0x00000777U 299 300 #define MSR_IA32_EXT_XAPICID 0x00000802U 301 #define MSR_IA32_EXT_APIC_VERSION 0x00000803U 302 #define MSR_IA32_EXT_APIC_TPR 0x00000808U 303 #define MSR_IA32_EXT_APIC_PPR 0x0000080AU 304 #define MSR_IA32_EXT_APIC_EOI 0x0000080BU 305 #define MSR_IA32_EXT_APIC_LDR 0x0000080DU 306 #define MSR_IA32_EXT_APIC_SIVR 0x0000080FU 307 #define MSR_IA32_EXT_APIC_ISR0 0x00000810U 308 #define MSR_IA32_EXT_APIC_ISR1 0x00000811U 309 #define MSR_IA32_EXT_APIC_ISR2 0x00000812U 310 #define MSR_IA32_EXT_APIC_ISR3 0x00000813U 311 #define MSR_IA32_EXT_APIC_ISR4 0x00000814U 312 #define MSR_IA32_EXT_APIC_ISR5 0x00000815U 313 #define MSR_IA32_EXT_APIC_ISR6 0x00000816U 314 #define MSR_IA32_EXT_APIC_ISR7 0x00000817U 315 #define MSR_IA32_EXT_APIC_TMR0 0x00000818U 316 #define MSR_IA32_EXT_APIC_TMR1 0x00000819U 317 #define MSR_IA32_EXT_APIC_TMR2 0x0000081AU 318 #define MSR_IA32_EXT_APIC_TMR3 0x0000081BU 319 #define MSR_IA32_EXT_APIC_TMR4 0x0000081CU 320 #define MSR_IA32_EXT_APIC_TMR5 0x0000081DU 321 #define MSR_IA32_EXT_APIC_TMR6 0x0000081EU 322 #define MSR_IA32_EXT_APIC_TMR7 0x0000081FU 323 #define MSR_IA32_EXT_APIC_IRR0 0x00000820U 324 #define MSR_IA32_EXT_APIC_IRR1 0x00000821U 325 #define MSR_IA32_EXT_APIC_IRR2 0x00000822U 326 #define MSR_IA32_EXT_APIC_IRR3 0x00000823U 327 #define MSR_IA32_EXT_APIC_IRR4 0x00000824U 328 #define MSR_IA32_EXT_APIC_IRR5 0x00000825U 329 #define MSR_IA32_EXT_APIC_IRR6 0x00000826U 330 #define MSR_IA32_EXT_APIC_IRR7 0x00000827U 331 #define MSR_IA32_EXT_APIC_ESR 0x00000828U 332 #define MSR_IA32_EXT_APIC_LVT_CMCI 0x0000082FU 333 #define MSR_IA32_EXT_APIC_ICR 0x00000830U 334 #define MSR_IA32_EXT_APIC_LVT_TIMER 0x00000832U 335 #define MSR_IA32_EXT_APIC_LVT_THERMAL 0x00000833U 336 #define MSR_IA32_EXT_APIC_LVT_PMI 0x00000834U 337 #define MSR_IA32_EXT_APIC_LVT_LINT0 0x00000835U 338 #define MSR_IA32_EXT_APIC_LVT_LINT1 0x00000836U 339 #define MSR_IA32_EXT_APIC_LVT_ERROR 0x00000837U 340 #define MSR_IA32_EXT_APIC_INIT_COUNT 0x00000838U 341 #define MSR_IA32_EXT_APIC_CUR_COUNT 0x00000839U 342 #define MSR_IA32_EXT_APIC_DIV_CONF 0x0000083EU 343 #define MSR_IA32_EXT_APIC_SELF_IPI 0x0000083FU 344 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80U 345 #define MSR_IA32_L3_QOS_CFG 0x00000C81U 346 #define MSR_IA32_L2_QOS_CFG 0x00000C82U 347 #define MSR_IA32_QM_EVTSEL 0x00000C8DU 348 #define MSR_IA32_QM_CTR 0x00000C8EU 349 #define MSR_IA32_PQR_ASSOC 0x00000C8FU 350 #define MSR_IA32_L3_MASK_BASE 0x00000C90U 351 #define MSR_IA32_XSS 0x00000DA0U 352 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0U 353 #define MSR_IA32_PM_CTL1 0x00000DB1U 354 #define MSR_IA32_THREAD_STALL 0x00000DB2U 355 #define MSR_IA32_L2_MASK_BASE 0x00000D10U 356 #define MSR_IA32_MBA_MASK_BASE 0x00000D50U 357 #define MSR_IA32_BNDCFGS 0x00000D90U 358 #define MSR_IA32_COPY_LOCAL_TO_PLATFORM 0x00000D91U 359 #define MSR_IA32_COPY_PLATFORM_TO_LOCAL 0x00000D92U 360 #define MSR_IA32_COPY_STATUS 0x00000990U 361 #define MSR_IA32_IWKEY_BACKUP_STATUS 0x00000991U 362 #define MSR_IA32_EFER 0xC0000080U 363 #define MSR_IA32_STAR 0xC0000081U 364 #define MSR_IA32_LSTAR 0xC0000082U 365 #define MSR_IA32_CSTAR 0xC0000083U 366 #define MSR_IA32_FMASK 0xC0000084U 367 #define MSR_IA32_FS_BASE 0xC0000100U 368 #define MSR_IA32_GS_BASE 0xC0000101U 369 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102U 370 #define MSR_IA32_TSC_AUX 0xC0000103U 371 372 /* non-architectural MSRs */ 373 #define MSR_EBL_CR_POWERON 0x0000002AU 374 #define MSR_EBC_SOFT_POWERON 0x0000002BU 375 #define MSR_EBC_FREQUENCY_ID 0x0000002CU 376 #define MSR_SMI_COUNT 0x00000034U 377 #define MSR_CORE_THREAD_COUNT 0x00000035U 378 #define MSR_LASTBRANCH_0_FROM_IP 0x00000040U 379 #define MSR_LASTBRANCH_1_FROM_IP 0x00000041U 380 #define MSR_LASTBRANCH_2_FROM_IP 0x00000042U 381 #define MSR_LASTBRANCH_3_FROM_IP 0x00000043U 382 #define MSR_LASTBRANCH_4_FROM_IP 0x00000044U 383 #define MSR_LASTBRANCH_5_FROM_IP 0x00000045U 384 #define MSR_LASTBRANCH_6_FROM_IP 0x00000046U 385 #define MSR_LASTBRANCH_7_FROM_IP 0x00000047U 386 #define MSR_PPIN_CTL 0x0000004EU 387 #define MSR_PPIN 0x0000004FU 388 #define MSR_THREAD_ID_INFO 0x00000053U 389 #define MSR_LASTBRANCH_0_TO_LIP 0x00000060U 390 #define MSR_LASTBRANCH_1_TO_LIP 0x00000061U 391 #define MSR_LASTBRANCH_2_TO_LIP 0x00000062U 392 #define MSR_LASTBRANCH_3_TO_LIP 0x00000063U 393 #define MSR_LASTBRANCH_4_TO_LIP 0x00000064U 394 #define MSR_LASTBRANCH_5_TO_LIP 0x00000065U 395 #define MSR_LASTBRANCH_6_TO_LIP 0x00000066U 396 #define MSR_LASTBRANCH_7_TO_LIP 0x00000067U 397 #define MSR_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080U 398 #define MSR_FSB_FREQ 0x000000CDU 399 #define MSR_PLATFORM_INFO 0x000000CEU 400 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000E2U 401 #define MSR_PMG_IO_CAPTURE_BASE 0x000000E4U 402 #define MSR_UNDOCUMENTED_TJMAX 0x000000EEU 403 #define MSR_BBL_CR_CTL 0x00000119U 404 #define MSR_BBL_CR_CTL3 0x0000011EU 405 #define MSR_FEATURE_CONFIG 0x0000013CU 406 #define MSR_SMM_MCA_CAP 0x0000017DU 407 #define MSR_ERROR_CONTROL 0x0000017FU 408 #define MSR_THERM2_CTL 0x0000019DU 409 #define MSR_PLATFORM_BRV 0x000001A1U 410 #define MSR_TEMPERATURE_TARGET 0x000001A2U 411 #define MSR_MISC_FEATURE_CONTROL 0x000001A4U 412 #define MSR_OFFCORE_RSP_0 0x000001A6U 413 #define MSR_OFFCORE_RSP_1 0x000001A7U 414 #define MSR_MISC_PWR_MGMT 0x000001AAU 415 #define MSR_TURBO_POWER_CURRENT_LIMIT 0x000001ACU 416 #define MSR_TURBO_RATIO_LIMIT 0x000001ADU 417 #define MSR_TURBO_GROUP_CORECNT 0x000001AEU 418 #define MSR_TURBO_RATIO_LIMIT2 0x000001AFU 419 #define MSR_LBR_SELECT 0x000001C8U 420 #define MSR_LASTBRANCH_TOS 0x000001DAU 421 #define MSR_LASTBRANCH_0 0x000001DBU 422 #define MSR_LASTBRANCH_1 0x000001DCU 423 #define MSR_LASTBRANCH_2 0x000001DDU 424 #define MSR_LASTBRANCH_3 0x000001DEU 425 #define MSR_PRMRR_PHYS_BASE 0x000001F4U 426 #define MSR_PRMRR_PHYS_MASK 0x000001F5U 427 #define MSR_PRMRR_VALID_CONFIG 0x000001FBU 428 #define MSR_POWER_CTL 0x000001FCU 429 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x000002F4U 430 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x000002F5U 431 432 #define MSR_BR_DETECT_CTRL 0x00000350U 433 #define MSR_BR_DETECT_STATUS 0x00000351U 434 #define MSR_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393U 435 #define MSR_UNCORE_FIXED_CTR0 0x00000394U 436 #define MSR_UNCORE_FIXED_CTR_CTRL 0x00000395U 437 #define MSR_UNCORE_ADDR_OPCODE_MATCH 0x00000396U 438 #define MSR_UNCORE_PMC0 0x000003B0U 439 #define MSR_UNCORE_PMC1 0x000003B1U 440 #define MSR_UNCORE_PMC2 0x000003B2U 441 #define MSR_UNCORE_PMC3 0x000003B3U 442 #define MSR_UNCORE_PMC4 0x000003B4U 443 #define MSR_UNCORE_PMC5 0x000003B5U 444 #define MSR_UNCORE_PMC6 0x000003B6U 445 #define MSR_UNCORE_PMC7 0x000003B7U 446 #define MSR_UNCORE_PERFEVTSEL0 0x000003C0U 447 #define MSR_UNCORE_PERFEVTSEL1 0x000003C1U 448 #define MSR_UNCORE_PERFEVTSEL2 0x000003C2U 449 #define MSR_UNCORE_PERFEVTSEL3 0x000003C3U 450 #define MSR_UNCORE_PERFEVTSEL4 0x000003C4U 451 #define MSR_UNCORE_PERFEVTSEL5 0x000003C5U 452 #define MSR_UNCORE_PERFEVTSEL6 0x000003C6U 453 #define MSR_UNCORE_PERFEVTSEL7 0x000003C7U 454 #define MSR_PEBS_LD_LAT 0x000003F6U 455 #define MSR_PEBS_FRONTEND 0x000003F7U 456 #define MSR_PKG_C2_RESIDENCY 0x000003F8U 457 #define MSR_PKG_C4_RESIDENCY 0x000003F9U 458 #define MSR_PKG_C6_RESIDENCY 0x000003FAU 459 #define MSR_CORE_C3_RESIDENCY 0x000003FCU 460 #define MSR_CORE_C6_RESIDENCY 0x000003FDU 461 #define MSR_CORE_C7_RESIDENCY 0x000003FEU 462 #define MSR_SMM_FEATURE_CONTROL 0x000004E0U 463 #define MSR_SMM_DELAYED 0x000004E2U 464 #define MSR_SMM_BLOCKED 0x000004E3U 465 #define MSR_RAPL_POWER_UNIT 0x00000606U 466 #define MSR_PKGC3_IRTL 0x0000060AU 467 #define MSR_PKGC_IRTL1 0x0000060BU 468 #define MSR_PKGC_IRTL2 0x0000060CU 469 #define MSR_ATOM_PKG_C2_RESIDENCY 0x0000060DU 470 #define MSR_PKG_POWER_LIMIT 0x00000610U 471 #define MSR_PKG_ENERGY_STATUS 0x00000611U 472 #define MSR_PKG_PERF_STATUS 0x00000613U 473 #define MSR_PKG_POWER_INFO 0x00000614U 474 #define MSR_DRAM_POWER_LIMIT 0x00000618U 475 #define MSR_DRAM_ENERGY_STATUS 0x00000619U 476 #define MSR_DRAM_PERF_STATUS 0x0000061BU 477 #define MSR_DRAM_POWER_INFO 0x0000061CU 478 #define MSR_PCIE_PLL_RATIO 0x0000061EU 479 #define MSR_UNCORE_RATIO_LIMIT 0x00000620U 480 #define MSR_PKG_C8_RESIDENCY 0x00000630U 481 #define MSR_PKG_C9_RESIDENCY 0x00000631U 482 #define MSR_PKG_C10_RESIDENCY 0x00000632U 483 #define MSR_PKGC8_IRTL 0x00000633U 484 #define MSR_PKGC9_IRTL 0x00000634U 485 #define MSR_PKGC10_IRTL 0x00000635U 486 #define MSR_PP0_POWER_LIMIT 0x00000638U 487 #define MSR_PP0_ENERGY_STATUS 0x00000639U 488 #define MSR_PP0_POLICY 0x0000063AU 489 #define MSR_PP1_POWER_LIMIT 0x00000640U 490 #define MSR_PP1_ENERGY_STATUS 0x00000641U 491 #define MSR_PP1_POLICY 0x00000642U 492 #define MSR_CONFIG_TDP_NOMINAL 0x00000648U 493 #define MSR_CONFIG_TDP_LEVEL1 0x00000649U 494 #define MSR_CONFIG_TDP_LEVEL2 0x0000064AU 495 #define MSR_CONFIG_TDP_CONTROL 0x0000064BU 496 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064CU 497 #define MSR_PLATFORM_ENERGY_COUNTER 0x0000064DU 498 #define MSR_PPERF 0x0000064EU 499 #define MSR_ATOM_CORE_PERF_LIMIT_REASONS 0X0000064FU 500 #define MSR_PKG_HDC_CONFIG 0x00000652U 501 #define MSR_CORE_HDC_RESIDENCY 0x00000653U 502 #define MSR_PKG_HDC_SHALLOW_RESIDENCY 0x00000655U 503 #define MSR_PKG_HDC_DEEP_RESIDENCY 0x00000656U 504 #define MSR_WEIGHTED_CORE_C0 0x00000658U 505 #define MSR_ANY_CORE_C0 0x00000659U 506 #define MSR_ANY_GFXE_C0 0x0000065AU 507 #define MSR_CORE_GFXE_OVERLAP_C0 0x0000065BU 508 #define MSR_PLATFORM_POWER_LIMIT 0x0000065CU 509 #define MSR_CORE_C1_RESIDENCY 0x00000660U 510 #define MSR_MC6_RESIDENCY_COUNTER 0x00000664U 511 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668U 512 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669U 513 #define MSR_ATOM_PKG_POWER_INFO 0x0000066EU 514 #define MSR_RING_PERF_LIMIT_REASONS 0x00000681U 515 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690U 516 #define MSR_LASTBRANCH_31_FROM_IP 0x0000069FU 517 #define MSR_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0U 518 #define MSR_LASTBRANCH_0_TO_IP 0x000006C0U 519 #define MSR_LASTBRANCH_31_TO_IP 0x000006DFU 520 #define MSR_IA32_L2_QOS_MASK_0 0x00000D10U 521 #define MSR_IA32_L2_QOS_MASK_1 0x00000D11U 522 #define MSR_IA32_L2_QOS_MASK_2 0x00000D12U 523 #define MSR_IA32_L2_QOS_MASK_3 0x00000D13U 524 #define MSR_LASTBRANCH_INFO_0 0x00000DC0U 525 #define MSR_LASTBRANCH_INFO_31 0x00000DDFU 526 #define MSR_R0_PMON_BOX_STATUS 0x00000E01U 527 #define MSR_EMON_L3_CTR_CTL0 0x000107CCU 528 #define MSR_EMON_L3_CTR_CTL1 0x000107CDU 529 #define MSR_EMON_L3_CTR_CTL2 0x000107CEU 530 #define MSR_EMON_L3_CTR_CTL3 0x000107CFU 531 #define MSR_EMON_L3_CTR_CTL4 0x000107D0U 532 #define MSR_EMON_L3_CTR_CTL5 0x000107D1U 533 #define MSR_EMON_L3_CTR_CTL6 0x000107D2U 534 #define MSR_EMON_L3_CTR_CTL7 0x000107D3U 535 536 #define IA32_HW_FEEDBACK_PTR 0x17d0U 537 #define IA32_HW_FEEDBACK_CONFIG 0x17d1U 538 #define IA32_THREAD_FEEDBACK_CHAR 0x17d2U 539 #define IA32_HW_FEEDBACK_THREAD_CONFIG 0x17d4U 540 541 #ifdef PROFILING_ON 542 /* Core (and Goldmont) specific MSRs */ 543 #define MSR_CORE_LASTBRANCH_TOS 0x000001C9U 544 /* Last branch record stack TOS */ 545 #define MSR_CORE_LASTBRANCH_0_FROM_IP 0x00000680U 546 /* Last branch record 0 from IP */ 547 #define MSR_CORE_LASTBRANCH_0_TO_IP 0x000006C0U 548 /* Last branch record 0 to IP */ 549 #endif 550 551 /* LINCROFT specific MSRs */ 552 #define MSR_LNC_BIOS_CACHE_AS_RAM 0x000002E0U /* Configure CAR */ 553 554 /* EFER bits */ 555 #define MSR_IA32_EFER_SCE_BIT (1UL << 0U) 556 #define MSR_IA32_EFER_LME_BIT (1UL << 8U) /* IA32e mode enable */ 557 #define MSR_IA32_EFER_LMA_BIT (1UL << 10U) /* IA32e mode active */ 558 #define MSR_IA32_EFER_NXE_BIT (1UL << 11U) 559 560 /* FEATURE CONTROL bits */ 561 #define MSR_IA32_FEATURE_CONTROL_LOCK (1U << 0U) 562 #define MSR_IA32_FEATURE_CONTROL_VMX_SMX (1U << 1U) 563 #define MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX (1U << 2U) 564 #define MSR_IA32_FEATURE_CONTROL_SENTERS_MSK (0x7F00U) 565 #define MSR_IA32_FEATURE_CONTROL_SENTER (1U << 15U) 566 #define MSR_IA32_FEATURE_CONTROL_SGX_LC (1U << 17U) 567 #define MSR_IA32_FEATURE_CONTROL_SGX_GE (1U << 18U) 568 569 /* PAT memory type definitions */ 570 #define PAT_MEM_TYPE_UC 0x00UL /* uncached */ 571 #define PAT_MEM_TYPE_WC 0x01UL /* write combining */ 572 #define PAT_MEM_TYPE_WT 0x04UL /* write through */ 573 #define PAT_MEM_TYPE_WP 0x05UL /* write protected */ 574 #define PAT_MEM_TYPE_WB 0x06UL /* writeback */ 575 #define PAT_MEM_TYPE_UCM 0x07UL /* uncached minus */ 576 577 /* MISC_ENABLE bits: architectural */ 578 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1UL << 0U) 579 #define MSR_IA32_MISC_ENABLE_TCC (1UL << 3U) 580 #define MSR_IA32_MISC_ENABLE_PMA (1UL << 7U) 581 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1UL << 11U) 582 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1UL << 12U) 583 #define MSR_IA32_MISC_ENABLE_TM2_ENABLE (1UL << 13U) 584 #define MSR_IA32_MISC_ENABLE_EIST (1UL << 16U) 585 #define MSR_IA32_MISC_ENABLE_MONITOR_ENA (1UL << 18U) 586 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1UL << 22U) 587 #define MSR_IA32_MISC_ENABLE_xTPR (1UL << 23U) 588 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1UL << 34U) 589 590 /* MSR_IA32_XSS bits */ 591 #define MSR_IA32_XSS_PT (1UL << 8U) 592 #define MSR_IA32_XSS_CET_U (1UL << 11U) 593 #define MSR_IA32_XSS_CET_S (1UL << 12U) 594 #define MSR_IA32_XSS_HDC (1UL << 13U) 595 596 /* Miscellaneous data */ 597 #define MSR_IA32_MISC_UNRESTRICTED_GUEST (1U<<5U) 598 599 /* Width of physical address used by VMX related region */ 600 #define MSR_IA32_VMX_BASIC_ADDR_WIDTH (1UL << 48U) 601 602 /* 5 high-order bits in every field are reserved */ 603 #define PAT_FIELD_RSV_BITS (0xF8UL) 604 /* MSR_TEST_CTL bits */ 605 #define MSR_TEST_CTL_GP_UCLOCK (1UL << 28U) 606 #define MSR_TEST_CTL_AC_SPLITLOCK (1UL << 29U) 607 #define MSR_TEST_CTL_DISABLE_LOCK_ASSERTION (1UL << 31U) 608 609 #ifndef ASSEMBLER is_pat_mem_type_invalid(uint64_t x)610static inline bool is_pat_mem_type_invalid(uint64_t x) 611 { 612 return (((x & PAT_FIELD_RSV_BITS) != 0UL) || ((x & 0x6UL) == 0x2UL)); 613 } 614 is_x2apic_msr(uint32_t msr)615static inline bool is_x2apic_msr(uint32_t msr) 616 { 617 /* 618 * if msr is in the range of x2APIC MSRs 619 */ 620 return ((msr >= 0x800U) && (msr < 0x900U)); 621 } 622 623 struct acrn_vcpu; 624 625 void init_msr_emulation(struct acrn_vcpu *vcpu); 626 void init_intercepted_cat_msr_list(void); 627 uint32_t vmsr_get_guest_msr_index(uint32_t msr); 628 void update_msr_bitmap_x2apic_apicv(struct acrn_vcpu *vcpu); 629 void update_msr_bitmap_x2apic_passthru(struct acrn_vcpu *vcpu); 630 631 #endif /* ASSEMBLER */ 632 633 #define PAT_POWER_ON_VALUE (PAT_MEM_TYPE_WB + \ 634 (PAT_MEM_TYPE_WT << 8U) + \ 635 (PAT_MEM_TYPE_UCM << 16U) + \ 636 (PAT_MEM_TYPE_UC << 24U) + \ 637 (PAT_MEM_TYPE_WB << 32U) + \ 638 (PAT_MEM_TYPE_WT << 40U) + \ 639 (PAT_MEM_TYPE_UCM << 48U) + \ 640 (PAT_MEM_TYPE_UC << 56U)) 641 642 #define PAT_ALL_UC_VALUE (PAT_MEM_TYPE_UC + \ 643 (PAT_MEM_TYPE_UC << 8U) + \ 644 (PAT_MEM_TYPE_UC << 16U) + \ 645 (PAT_MEM_TYPE_UC << 24U) + \ 646 (PAT_MEM_TYPE_UC << 32U) + \ 647 (PAT_MEM_TYPE_UC << 40U) + \ 648 (PAT_MEM_TYPE_UC << 48U) + \ 649 (PAT_MEM_TYPE_UC << 56U)) 650 651 /* MTRR memory type definitions */ 652 #define MTRR_MEM_TYPE_UC 0x00UL /* uncached */ 653 #define MTRR_MEM_TYPE_WC 0x01UL /* write combining */ 654 #define MTRR_MEM_TYPE_WT 0x04UL /* write through */ 655 #define MTRR_MEM_TYPE_WP 0x05UL /* write protected */ 656 #define MTRR_MEM_TYPE_WB 0x06UL /* writeback */ 657 658 /* misc. MTRR flag definitions */ 659 #define MTRR_ENABLE 0x800U /* MTRR enable */ 660 #define MTRR_FIX_ENABLE 0x400U /* fixed range MTRR enable */ 661 #define MTRR_VALID 0x800U /* MTRR setting is valid */ 662 663 /* SPEC & PRED bit */ 664 #define SPEC_ENABLE_IBRS (1U << 0U) 665 #define SPEC_ENABLE_STIBP (1U << 1U) 666 #define SPEC_RRSBA_DIS_S (1U << 6U) 667 #define PRED_SET_IBPB (1U << 0U) 668 669 /* IA32 ARCH Capabilities bit */ 670 #define IA32_ARCH_CAP_RDCL_NO (1UL << 0U) 671 #define IA32_ARCH_CAP_IBRS_ALL (1UL << 1U) 672 #define IA32_ARCH_CAP_RSBA (1UL << 2U) 673 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY (1UL << 3U) 674 #define IA32_ARCH_CAP_SSB_NO (1UL << 4U) 675 #define IA32_ARCH_CAP_MDS_NO (1UL << 5U) 676 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO (1UL << 6U) 677 #define IA32_ARCH_CAP_RESTRICTED_RSBA (1UL << 19U) 678 679 /* Flush L1 D-cache */ 680 #define IA32_L1D_FLUSH (1UL << 0U) 681 682 /* PLATFORM INFO bits */ 683 #define MSR_PLATFORM_INFO_MAX_NON_TURBO_LIM_RATIO_MASK (0x000000000000ff00UL) /* 15:8 */ 684 #define MSR_PLATFORM_INFO_MAX_EFFICIENCY_RATIO_MASK (0x0000ff0000000000UL) /* 47:40 */ 685 #define MSR_PLATFORM_INFO_MIN_OPERATING_RATIO_MASK (0x00ff000000000000UL) /* 55:48 */ 686 #define MSR_PLATFORM_INFO_SAMPLE_PART (1UL << 27U) 687 688 #define MSR_IA32_HWP_STATUS_RSV_BITS (~0x3DUL) 689 #define MSR_IA32_HWP_REQUEST_RSV_BITS (0x7FFF80000000000UL) 690 #define MSR_IA32_HWP_REQUEST_PKG_CTL (1UL << 42U) 691 692 /* Thermal MSR reserved bits */ 693 #define MSR_IA32_CLOCK_MODULATION_RSV_BITS (~0x1FUL) 694 #define MSR_IA32_THERM_STATUS_RSV_BITS (~0xAAAUL) 695 #define MSR_IA32_THERM_INTERRUPT_RSV_BITS (~0x1FFFF1FUL) 696 #define MSR_IA32_PACKAGE_THERM_STATUS_RSV_BITS (~0xAA2UL) 697 #define MSR_IA32_PACKAGE_THERM_INTERRUPT_RSV_BITS (~0x1FFFF17UL) 698 699 #endif /* MSR_H */ 700