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Searched refs:MSR_IA32_L3_MASK_BASE (Results 1 – 3 of 3) sorted by relevance

/hypervisor/arch/x86/guest/
A Dvmsr.c471 if ((msr >= MSR_IA32_L3_MASK_BASE) && (msr < (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS))) { in cat_msr_to_index_of_emulated_msr()
472 index = msr - MSR_IA32_L3_MASK_BASE; in cat_msr_to_index_of_emulated_msr()
505 for (msr = MSR_IA32_L3_MASK_BASE; msr < (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS); msr++) { in init_intercepted_cat_msr_list()
545 for (msr = MSR_IA32_L3_MASK_BASE; msr < MSR_IA32_BNDCFGS; msr++) { in init_msr_emulation()
849 case MSR_IA32_L3_MASK_BASE ... (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS - 1U): in rdmsr_vmexit_handler()
1333 case MSR_IA32_L3_MASK_BASE ... (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS - 1U): in wrmsr_vmexit_handler()
A Dvcat.c197 && (vmsr >= MSR_IA32_L3_MASK_BASE) && (vmsr < (MSR_IA32_L3_MASK_BASE + num_vcbm_msrs))); in is_l3_vcbm_msr()
323 msr_base = MSR_IA32_L3_MASK_BASE; in write_vcbm()
471 init_vcbms(vcpu, RDT_RESOURCE_L3, MSR_IA32_L3_MASK_BASE); in init_vcat_msrs()
/hypervisor/include/arch/x86/asm/
A Dmsr.h350 #define MSR_IA32_L3_MASK_BASE 0x00000C90U macro

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