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Searched refs:NUM_CAT_L3_MSRS (Results 1 – 2 of 2) sorted by relevance

/hypervisor/arch/x86/guest/
A Dvmsr.c471 if ((msr >= MSR_IA32_L3_MASK_BASE) && (msr < (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS))) { in cat_msr_to_index_of_emulated_msr()
474 index = msr - MSR_IA32_L2_MASK_BASE + NUM_CAT_L3_MSRS; in cat_msr_to_index_of_emulated_msr()
476 index = NUM_CAT_L3_MSRS + NUM_CAT_L2_MSRS; in cat_msr_to_index_of_emulated_msr()
505 for (msr = MSR_IA32_L3_MASK_BASE; msr < (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS); msr++) { in init_intercepted_cat_msr_list()
849 case MSR_IA32_L3_MASK_BASE ... (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS - 1U): in rdmsr_vmexit_handler()
1333 case MSR_IA32_L3_MASK_BASE ... (MSR_IA32_L3_MASK_BASE + NUM_CAT_L3_MSRS - 1U): in wrmsr_vmexit_handler()
/hypervisor/include/arch/x86/asm/guest/
A Dvcpu.h182 #define NUM_CAT_L3_MSRS MAX_CACHE_CLOS_NUM_ENTRIES macro
185 #define NUM_CAT_MSRS (NUM_CAT_L2_MSRS + NUM_CAT_L3_MSRS + 1U)

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