1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CPUFEATURES_H 8 #define CPUFEATURES_H 9 10 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/ 11 #define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5U) + 0U) 12 #define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5U) + 1U) 13 #define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5U) + 2U) 14 #define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5U) + 3U) 15 #define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5U) + 4U) 16 #define X86_FEATURE_VMX ((FEAT_1_ECX << 5U) + 5U) 17 #define X86_FEATURE_SMX ((FEAT_1_ECX << 5U) + 6U) 18 #define X86_FEATURE_EST ((FEAT_1_ECX << 5U) + 7U) 19 #define X86_FEATURE_TM2 ((FEAT_1_ECX << 5U) + 8U) 20 #define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5U) + 9U) 21 #define X86_FEATURE_CID ((FEAT_1_ECX << 5U) + 10U) 22 #define X86_FEATURE_FMA ((FEAT_1_ECX << 5U) + 12U) 23 #define X86_FEATURE_CX16 ((FEAT_1_ECX << 5U) + 13U) 24 #define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5U) + 14U) 25 #define X86_FEATURE_PDCM ((FEAT_1_ECX << 5U) + 15U) 26 #define X86_FEATURE_PCID ((FEAT_1_ECX << 5U) + 17U) 27 #define X86_FEATURE_DCA ((FEAT_1_ECX << 5U) + 18U) 28 #define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5U) + 19U) 29 #define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5U) + 20U) 30 #define X86_FEATURE_X2APIC ((FEAT_1_ECX << 5U) + 21U) 31 #define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5U) + 22U) 32 #define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5U) + 23U) 33 #define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5U) + 24U) 34 #define X86_FEATURE_AES ((FEAT_1_ECX << 5U) + 25U) 35 #define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5U) + 26U) 36 #define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5U) + 27U) 37 #define X86_FEATURE_AVX ((FEAT_1_ECX << 5U) + 28U) 38 #define X86_FEATURE_RDRAND ((FEAT_1_ECX << 5U) + 30U) 39 40 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX)*/ 41 #define X86_FEATURE_FPU ((FEAT_1_EDX << 5U) + 0U) 42 #define X86_FEATURE_VME ((FEAT_1_EDX << 5U) + 1U) 43 #define X86_FEATURE_DE ((FEAT_1_EDX << 5U) + 2U) 44 #define X86_FEATURE_PSE ((FEAT_1_EDX << 5U) + 3U) 45 #define X86_FEATURE_TSC ((FEAT_1_EDX << 5U) + 4U) 46 #define X86_FEATURE_MSR ((FEAT_1_EDX << 5U) + 5U) 47 #define X86_FEATURE_PAE ((FEAT_1_EDX << 5U) + 6U) 48 #define X86_FEATURE_MCE ((FEAT_1_EDX << 5U) + 7U) 49 #define X86_FEATURE_CX8 ((FEAT_1_EDX << 5U) + 8U) 50 #define X86_FEATURE_APIC ((FEAT_1_EDX << 5U) + 9U) 51 #define X86_FEATURE_SEP ((FEAT_1_EDX << 5U) + 11U) 52 #define X86_FEATURE_MTRR ((FEAT_1_EDX << 5U) + 12U) 53 #define X86_FEATURE_PGE ((FEAT_1_EDX << 5U) + 13U) 54 #define X86_FEATURE_MCA ((FEAT_1_EDX << 5U) + 14U) 55 #define X86_FEATURE_CMOV ((FEAT_1_EDX << 5U) + 15U) 56 #define X86_FEATURE_PAT ((FEAT_1_EDX << 5U) + 16U) 57 #define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5U) + 17U) 58 #define X86_FEATURE_PSN ((FEAT_1_EDX << 5U) + 18U) 59 #define X86_FEATURE_CLF ((FEAT_1_EDX << 5U) + 19U) 60 #define X86_FEATURE_DTES ((FEAT_1_EDX << 5U) + 21U) 61 #define X86_FEATURE_ACPI ((FEAT_1_EDX << 5U) + 22U) 62 #define X86_FEATURE_MMX ((FEAT_1_EDX << 5U) + 23U) 63 #define X86_FEATURE_FXSR ((FEAT_1_EDX << 5U) + 24U) 64 #define X86_FEATURE_SSE ((FEAT_1_EDX << 5U) + 25U) 65 #define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5U) + 26U) 66 #define X86_FEATURE_SS ((FEAT_1_EDX << 5U) + 27U) 67 #define X86_FEATURE_HTT ((FEAT_1_EDX << 5U) + 28U) 68 #define X86_FEATURE_TM1 ((FEAT_1_EDX << 5U) + 29U) 69 #define X86_FEATURE_IA64 ((FEAT_1_EDX << 5U) + 30U) 70 #define X86_FEATURE_PBE ((FEAT_1_EDX << 5U) + 31U) 71 72 /* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/ 73 #define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5U) + 1U) 74 #define X86_FEATURE_SGX ((FEAT_7_0_EBX << 5U) + 2U) 75 #define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5U) + 7U) 76 #define X86_FEATURE_ERMS ((FEAT_7_0_EBX << 5U) + 9U) 77 #define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U) 78 #define X86_FEATURE_RDT_A ((FEAT_7_0_EBX << 5U) + 15U) 79 #define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U) 80 #define X86_FEATURE_CLFLUSHOPT ((FEAT_7_0_EBX << 5U) + 23U) 81 82 /* Intel-defined CPU features, CPUID level 0x00000007 (ECX)*/ 83 #define X86_FEATURE_WAITPKG ((FEAT_7_0_ECX << 5U) + 5U) 84 #define X86_FEATURE_KEYLOCKER ((FEAT_7_0_ECX << 5U) + 23U) 85 86 /* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/ 87 #define X86_FEATURE_MDS_CLEAR ((FEAT_7_0_EDX << 5U) + 10U) 88 #define X86_FEATURE_HYBRID ((FEAT_7_0_EDX << 5U) + 15U) 89 #define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5U) + 26U) 90 #define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5U) + 27U) 91 #define X86_FEATURE_L1D_FLUSH ((FEAT_7_0_EDX << 5U) + 28U) 92 #define X86_FEATURE_ARCH_CAP ((FEAT_7_0_EDX << 5U) + 29U) 93 #define X86_FEATURE_CORE_CAP ((FEAT_7_0_EDX << 5U) + 30U) 94 #define X86_FEATURE_SSBD ((FEAT_7_0_EDX << 5U) + 31U) 95 96 /* Intel-defined CPU features, CPUID level 0x00000007, sub 0x2 (EDX)*/ 97 #define X86_FEATURE_RRSBA_CTRL ((FEAT_7_2_EDX << 5U) + 2U) 98 99 /* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/ 100 #define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5U) + 20U) 101 #define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U) 102 #define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U) 103 104 /* Intel-defined CPU features, CPUID level 0x80000007 (EDX)*/ 105 #define X86_FEATURE_INVA_TSC ((FEAT_8000_0007_EDX << 5U) + 8U) 106 107 /* Intel-defined CPU features, CPUID level 0x0000000D, sub 0x1 */ 108 #define X86_FEATURE_COMPACTION_EXT ((FEAT_D_1_EAX << 5U) + 1U) 109 #define X86_FEATURE_XSAVES ((FEAT_D_1_EAX << 5U) + 3U) 110 111 #endif /* CPUFEATURES_H */ 112