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Searched refs:base (Results 1 – 25 of 35) sorted by relevance

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/hypervisor/dm/vpci/
A Dvdev.c100 return ((base >= res->start) && (base <= res->end)); in is_pci_mem_bar_base_valid()
106 uint64_t base = 0UL; in pci_vdev_update_vbar_base() local
114 base = lo & vbar->mask; in pci_vdev_update_vbar_base()
120 base |= ((uint64_t)hi << 32U); in pci_vdev_update_vbar_base()
122 base = 0UL; in pci_vdev_update_vbar_base()
130 base &= 0xffffUL; in pci_vdev_update_vbar_base()
134 if (base != 0UL) { in pci_vdev_update_vbar_base()
150 base = 0UL; in pci_vdev_update_vbar_base()
153 if ((!is_pci_mem_bar_base_valid(vpci2vm(vdev->vpci), base)) in pci_vdev_update_vbar_base()
154 || (!mem_aligned_check(base, vdev->vbars[idx].size))) { in pci_vdev_update_vbar_base()
[all …]
/hypervisor/arch/x86/lib/
A Dmemory.c7 static inline void memset_erms(void *base, uint8_t v, size_t n) in memset_erms() argument
10 : "+D"(base) in memset_erms()
14 void *memset(void *base, uint8_t v, size_t n) in memset() argument
20 if ((base != NULL) && (n != 0U)) { in memset()
21 memset_erms(base, v, n); in memset()
24 return base; in memset()
/hypervisor/debug/
A Dstring.c19 uint64_t base = 10UL; in strtol_deci() local
58 cutlim = cutoff % base; in strtol_deci()
59 cutoff /= base; in strtol_deci()
70 acc *= base; in strtol_deci()
A Dnpk_log.c17 static uint64_t base; variable
96 base = param->mmio_addr; in npk_log_setup()
101 if ((base != 0UL) && (param->cmd == HV_NPK_LOG_CMD_ENABLE)) { in npk_log_setup()
107 set_paging_supervisor(base, in npk_log_setup()
123 param->mmio_addr = base; in npk_log_setup()
138 struct npk_chan *channel = (struct npk_chan *)base; in npk_log_write()
/hypervisor/arch/x86/
A Dsgx.c23 static int32_t get_epc_section(uint32_t sec_id, uint64_t* base, uint64_t* size) in get_epc_section() argument
31 *base = (((uint64_t)ebx & CPUID_SGX_EPC_HIGH_MASK) << 32U) | in get_epc_section()
36 pepc_sections[sec_id].base = *base; in get_epc_section()
86 vm_epc_maps[mid][vm_id].gpa = vm_config->epc.base + vm_config->epc.size - vm_request_size; in partition_epc()
A Drtcm.c78 ssram_top_hpa = max(ssram_top_hpa, ssram->base + ssram->size); in parse_rtct()
79 bottom_hpa = min(bottom_hpa, ssram->base); in parse_rtct()
81 ssram->cache_level, ssram->base, ssram->size); in parse_rtct()
93 ssram_top_hpa = max(ssram_top_hpa, ssram_v2->base + ssram_v2->size); in parse_rtct()
94 bottom_hpa = min(bottom_hpa, ssram_v2->base); in parse_rtct()
96 ssram_v2->cache_level, ssram_v2->base, ssram_v2->size); in parse_rtct()
A Dmmu.c199 void set_paging_supervisor(uint64_t base, uint64_t size) in set_paging_supervisor() argument
203 uint64_t region_end = base + size; in set_paging_supervisor()
206 base_aligned = round_pde_down(base); in set_paging_supervisor()
213 void set_paging_nx(uint64_t base, uint64_t size) in set_paging_nx() argument
215 uint64_t region_end = base + size; in set_paging_nx()
216 uint64_t base_aligned = round_pde_down(base); in set_paging_nx()
223 void set_paging_x(uint64_t base, uint64_t size) in set_paging_x() argument
225 uint64_t region_end = base + size; in set_paging_x()
226 uint64_t base_aligned = round_pde_down(base); in set_paging_x()
A Dlapic.c83 union lapic_base_msr base; in early_init_lapic() local
86 base.value = msr_read(MSR_IA32_APIC_BASE); in early_init_lapic()
94 base.fields.xAPIC_enable = 1U; in early_init_lapic()
95 msr_write(MSR_IA32_APIC_BASE, base.value); in early_init_lapic()
97 base.fields.x2APIC_enable = 1U; in early_init_lapic()
98 msr_write(MSR_IA32_APIC_BASE, base.value); in early_init_lapic()
/hypervisor/arch/x86/guest/
A Dguest_memory.c61 void *base; in local_gva2gpa_common() local
80 base = gpa2hva(vcpu->vm, addr); in local_gva2gpa_common()
81 if (base == NULL) { in local_gva2gpa_common()
89 uint32_t *base32 = (uint32_t *)base; in local_gva2gpa_common()
93 uint64_t *base64 = (uint64_t *)base; in local_gva2gpa_common()
174 uint64_t *base; in local_gva2gpa_pae() local
180 base = (uint64_t *)gpa2hva(vcpu->vm, addr); in local_gva2gpa_pae()
181 if (base != NULL) { in local_gva2gpa_pae()
184 entry = base[index]; in local_gva2gpa_pae()
A Dvm_reset.c216 io_range.base = 0x64U; in register_reset_port_handler()
220 io_range.base = 0xcf9U; in register_reset_port_handler()
233 io_range.base = (uint16_t)reset_reg->reg.address; in register_reset_port_handler()
A Dvcpu.c350 seg->base = 0UL; in set_vcpu_regs()
359 ectx->cs.base = vcpu_regs->cs_base; in set_vcpu_regs()
362 ectx->gdtr.base = vcpu_regs->gdt.base; in set_vcpu_regs()
365 ectx->idtr.base = vcpu_regs->idt.base; in set_vcpu_regs()
376 ectx->ldtr.base = 0UL; in set_vcpu_regs()
377 ectx->tr.base = 0UL; in set_vcpu_regs()
411 .base = 0UL,
415 .base = 0UL,
487 vcpu_regs.gdt.base = vgdt_base_gpa; in init_vcpu_protect_mode_regs()
500 ectx->cs.base = ectx->cs.selector << 4U; in set_vcpu_startup_entry()
A Dvm.c411 uint64_t base = 0UL, size = 0UL, mask; in deny_pci_bar_access() local
419 base = pdev->bars[idx].phy_bar; in deny_pci_bar_access()
423 base |= (((uint64_t)pdev->bars[idx].phy_bar) << 32UL); in deny_pci_bar_access()
428 base &= mask; in deny_pci_bar_access()
432 if ((base != 0UL)) { in deny_pci_bar_access()
434 base &= 0xffffU; in deny_pci_bar_access()
435 deny_guest_pio_access(service_vm, base, size); in deny_pci_bar_access()
438 ASSERT((base & PAGE_MASK) != 0U, "%02x:%02x.%d bar[%d] 0x%lx, is not 4K aligned!", in deny_pci_bar_access()
439 pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f, idx, base); in deny_pci_bar_access()
441 ept_del_mr(service_vm, pml4_page, base, size); in deny_pci_bar_access()
[all …]
A Dpm.c257 gas_io.base = (uint16_t)gas->address; in register_gas_io_handler()
262 pr_dbg("Enable PM1A trap for VM %d, port 0x%x, size %d\n", vm->vm_id, gas_io.base, gas_io.len); in register_gas_io_handler()
307 io_range.base = VIRTUAL_PM1A_CNT_ADDR; in register_rt_vm_pm1a_ctl_handler()
374 io_range.base = VIRTUAL_SLEEP_CTL_ADDR; in register_prelaunched_vm_sleep_handler()
A Dinstr_emul.c258 uint64_t base; member
502 desc->base = exec_vmread(tdesc.base_field); in vm_get_seg_desc()
586 segbase = desc->base; in vie_calculate_gla()
2021 vie->base = (x >> 0U) & 0x7U; in decode_sib()
2025 vie->base |= vie->rex_b << 3U; in decode_sib()
2049 if ((vie->mod == VIE_MOD_INDIRECT) && ((vie->base == 5U) || (vie->base == 13U))) { in decode_sib()
2278 uint64_t base, segbase, idx, gva, gpa; in instr_check_gva() local
2283 base = 0UL; in instr_check_gva()
2285 base = vm_get_register(vcpu, vie->base_register); in instr_check_gva()
2291 base += vie->num_processed; in instr_check_gva()
[all …]
A Dtrusty.c142 ext_ctx->idtr.base = exec_vmread(VMX_GUEST_IDTR_BASE); in save_world_ctx()
143 ext_ctx->gdtr.base = exec_vmread(VMX_GUEST_GDTR_BASE); in save_world_ctx()
195 exec_vmwrite(VMX_GUEST_IDTR_BASE, ext_ctx->idtr.base); in load_world_ctx()
196 exec_vmwrite(VMX_GUEST_GDTR_BASE, ext_ctx->gdtr.base); in load_world_ctx()
A Dvmcs.c35 exec_vmwrite(VMX_GUEST_GDTR_BASE, ectx->gdtr.base); in init_guest_vmx()
36 pr_dbg("VMX_GUEST_GDTR_BASE: 0x%016lx", ectx->gdtr.base); in init_guest_vmx()
40 exec_vmwrite(VMX_GUEST_IDTR_BASE, ectx->idtr.base); in init_guest_vmx()
41 pr_dbg("VMX_GUEST_IDTR_BASE: 0x%016lx", ectx->idtr.base); in init_guest_vmx()
/hypervisor/include/arch/x86/asm/
A Dmmu.h150 void set_paging_supervisor(uint64_t base, uint64_t size);
151 void set_paging_x(uint64_t base, uint64_t size);
152 void set_paging_nx(uint64_t base, uint64_t size);
A Drtct.h67 uint64_t base; member
76 uint64_t base; member
A Dsgx.h34 uint64_t base; /* EPC section base, must be page aligned */ member
A Dcpu.h311 uint64_t base; member
330 uint64_t base; member
502 return gdtb.base; in sgdt()
509 return idtb.base; in sidt()
/hypervisor/lib/
A Dstring.c32 uint64_t base = 16UL; in strtoul_hex() local
48 cutoff = ULONG_MAX / base; in strtoul_hex()
49 cutlim = ULONG_MAX % base; in strtoul_hex()
58 acc *= base; in strtoul_hex()
/hypervisor/dm/
A Dio_req.c652 uint64_t address, size, base, end; in hv_emulate_mmio() local
669 base = mmio_handler->range_start; in hv_emulate_mmio()
672 if (((address + size) <= base) || (address >= end)) { in hv_emulate_mmio()
675 if ((address >= base) && ((address + size) <= end)) { in hv_emulate_mmio()
798 deny_guest_pio_access(vm, range->base, range->len); in register_pio_emulation_handler()
800 vm->emul_pio[pio_idx].port_start = range->base; in register_pio_emulation_handler()
801 vm->emul_pio[pio_idx].port_end = range->base + range->len; in register_pio_emulation_handler()
/hypervisor/include/arch/x86/asm/guest/
A Dinstr_emul.h70 base:4; member
/hypervisor/include/lib/
A Drtl.h43 void *memset(void *base, uint8_t v, size_t n);
/hypervisor/boot/
A Dacpi_base.c41 static struct acpi_table_rsdp *found_rsdp(char *base, uint64_t length) in found_rsdp() argument
48 rsdp = (struct acpi_table_rsdp *)(base + ofs); in found_rsdp()

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