cache_level (reference) in projects: hypervisor

Searched refs:cache_level (Results 1 – 4 of 4) sorted by relevance

/hypervisor/include/arch/x86/asm/
A D	rtct.h	`66 uint32_t cache_level; member 74 uint32_t cache_level; member`
/hypervisor/arch/x86/
A D	rtcm.c	`81 ssram->cache_level, ssram->base, ssram->size); in parse_rtct() 96 ssram_v2->cache_level, ssram_v2->base, ssram_v2->size); in parse_rtct()`
/hypervisor/common/
A D	hypercall.c	`156 uint32_t cache_type, cache_level, id, shift; in get_cache_shift() local 161 cache_level = (eax >> 5U) & 0x7U; in get_cache_shift() 170 if (cache_level == 2U) { in get_cache_shift() 172 } else if (cache_level == 3U) { in get_cache_shift()`
/hypervisor/arch/x86/guest/
A D	vcpuid.c	`245 uint32_t cache_level = (entry->eax >> 5U) & 0x7U; /* EAX bits 07:05 */ in set_vcpuid_vcat_04h() local 248 if (cache_level == 2U) { in set_vcpuid_vcat_04h() 250 } else if (cache_level == 3U) { in set_vcpuid_vcat_04h()`

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