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Searched refs:cap (Results 1 – 7 of 7) sorted by relevance

/hypervisor/include/arch/x86/asm/
A Dvtd.h94 return ((uint8_t)(cap >> 59U) & 1U); in iommu_cap_pi()
99 return ((uint8_t)(cap >> 55U) & 1U); in iommu_cap_read_drain()
104 return ((uint8_t)(cap >> 54U) & 1U); in iommu_cap_write_drain()
119 return ((uint8_t)(cap >> 39U) & 1U); in iommu_cap_pgsel_inv()
124 return ((uint8_t)(cap >> 34U) & 0xfU); in iommu_cap_super_page_val()
140 return ((uint8_t)(cap >> 22U) & 1U); in iommu_cap_zlr()
145 return ((uint8_t)(cap >> 23U) & 1U); in iommu_cap_isoch()
160 return ((uint8_t)(cap >> 7U) & 1U); in iommu_cap_caching_mode()
165 return ((uint8_t)(cap >> 6U) & 1U); in iommu_cap_phmr()
170 return ((uint8_t)(cap >> 5U) & 1U); in iommu_cap_plmr()
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/hypervisor/arch/x86/guest/
A Dvmtrr.c84 return ((vmtrr->cap.bits.fix != 0U) && in is_fixed_range_mtrr_enabled()
97 union mtrr_cap_reg cap = {0}; in init_vmtrr() local
105 vmtrr->cap.bits.vcnt = 0U; in init_vmtrr()
106 vmtrr->cap.bits.fix = 1U; in init_vmtrr()
112 cap.value = msr_read(MSR_IA32_MTRR_CAP); in init_vmtrr()
116 if (cap.bits.fix != 0U) { in init_vmtrr()
257 ret = vmtrr->cap.value; in read_vmtrr()
/hypervisor/arch/x86/
A Dvtd.c137 uint64_t cap; member
274 static inline uint8_t iommu_cap_rwbf(uint64_t cap) in iommu_cap_rwbf() argument
276 return ((uint8_t)(cap >> 4U) & 1U); in iommu_cap_rwbf()
287 pr_info("\tNumDomain:%d", iommu_cap_ndoms(dmar_unit->cap)); in dmar_unit_show_capability()
293 pr_info("\tSAGAW:0x%x", iommu_cap_sagaw(dmar_unit->cap)); in dmar_unit_show_capability()
294 pr_info("\tMGAW:%d", iommu_cap_mgaw(dmar_unit->cap)); in dmar_unit_show_capability()
295 pr_info("\tZeroLenRead:%d", iommu_cap_zlr(dmar_unit->cap)); in dmar_unit_show_capability()
342 uint8_t sgaw = iommu_cap_sagaw(dmar_unit->cap); in dmar_unit_get_msagw()
359 return (((1U << aw) & iommu_cap_sagaw(dmar_unit->cap)) != 0U); in dmar_unit_support_aw()
439 dmar_unit->cap = iommu_read64(dmar_unit, DMAR_CAP_REG); in dmar_register_hrhd()
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/hypervisor/hw/
A Dpci.c671 uint32_t ctrl = 0, cap; in pci_enable_ptm_root() local
673 cap = pci_pdev_read_cfg(pdev->bdf, pos + PCIR_PTM_CAP, PCI_PTM_CAP_LEN); in pci_enable_ptm_root()
675 if (cap & PCIM_PTM_CAP_ROOT_CAPABLE) { in pci_enable_ptm_root()
775 uint8_t pos, cap; in pci_enumerate_cap() local
785 cap = (uint8_t)pci_pdev_read_cfg(pdev->bdf, pos + PCICAP_ID, 1U); in pci_enumerate_cap()
787 if (cap == PCIY_MSI) { in pci_enumerate_cap()
789 } else if (cap == PCIY_MSIX) { in pci_enumerate_cap()
808 pdev->msix.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, (uint32_t)pos + idx, 1U); in pci_enumerate_cap()
810 } else if (cap == PCIY_PMC) { in pci_enumerate_cap()
813 } else if (cap == PCIY_PCIE) { in pci_enumerate_cap()
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/hypervisor/include/arch/x86/asm/guest/
A Dvmtrr.h51 union mtrr_cap_reg cap; member
/hypervisor/include/hw/
A Dpci.h264 uint8_t cap[MSIX_CAPLEN]; member
/hypervisor/dm/vpci/
A Dpci_pt.c534 (void *)&pdev->msix.cap[0U], pdev->msix.caplen); in init_vmsix_pt()

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