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Searched refs:msix (Results 1 – 11 of 11) sorted by relevance

/hypervisor/dm/vpci/
A Dvmsix.c56 vdev->msix.table_count = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U; in read_vmsix_cap_reg()
105 offset = mmio->address - vdev->msix.mmio_gpa; in rw_vmsix_table()
110 table_offset = (uint32_t)(offset - vdev->msix.table_offset); in rw_vmsix_table()
113 entry = &vdev->msix.table_entries[index]; in rw_vmsix_table()
128 hva = hpa2hva(vdev->msix.mmio_hpa + (mmio->address - vdev->msix.mmio_gpa)); in rw_vmsix_table()
171 vdev->msix.caplen = MSIX_CAPLEN; in add_vmsix_capability()
172 vdev->msix.table_bar = bar_num; in add_vmsix_capability()
173 vdev->msix.table_offset = 0U; in add_vmsix_capability()
174 vdev->msix.table_count = entry_num; in add_vmsix_capability()
178 vdev->msix.table_entries[i].vector_control |= PCIM_MSIX_VCTRL_MASK; in add_vmsix_capability()
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A Dpci_pt.c45 void *hva = hpa2hva(vdev->msix.mmio_hpa + vdev->msix.table_offset); in get_msix_table_entry()
178 struct pci_msix *msix = &vdev->msix; in vdev_pt_unmap_msix() local
188 addr_lo = msix->mmio_gpa + msix->table_offset; in vdev_pt_unmap_msix()
205 struct pci_msix *msix = &vdev->msix; in vdev_pt_map_msix() local
514 vdev->msix.mmio_size = vdev->vbars[vdev->msix.table_bar].size; in init_bars()
526 vdev->msix.capoff = pdev->msix.capoff; in init_vmsix_pt()
527 vdev->msix.caplen = pdev->msix.caplen; in init_vmsix_pt()
528 vdev->msix.table_bar = pdev->msix.table_bar; in init_vmsix_pt()
529 vdev->msix.table_offset = pdev->msix.table_offset; in init_vmsix_pt()
530 vdev->msix.table_count = pdev->msix.table_count; in init_vmsix_pt()
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A Dvmsix_on_msi.c67 return vdev->msi.is_64bit ? (vdev->msix.capoff + 0x10U) : (vdev->msix.capoff + 0xCU); in get_mask_bits_offset()
91 vdev->msix.capoff = pdev->msi_capoff; in init_vmsix_on_msi()
93 vdev->msix.is_vmsix_on_msi = true; in init_vmsix_on_msi()
95 vdev->msix.caplen = MSIX_CAPLEN; in init_vmsix_on_msi()
96 vdev->msix.table_bar = i; in init_vmsix_on_msi()
97 vdev->msix.table_offset = 0U; in init_vmsix_on_msi()
98 vdev->msix.table_count = pdev->irte_count; in init_vmsix_on_msi()
168 uint32_t capoff = vdev->msix.capoff; in remap_one_vmsix_entry_on_msi()
174 ventry = &vdev->msix.table_entries[index]; in remap_one_vmsix_entry_on_msi()
182 if (!vdev->msix.is_vmsix_on_msi_programmed) { in remap_one_vmsix_entry_on_msi()
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A Dvpci_priv.h64 return (vdev->msix.capoff != 0U); in has_msix_cap()
72 return (has_msix_cap(vdev) && in_range(offset, vdev->msix.capoff, vdev->msix.caplen)); in msixcap_access()
80 return in_range(offset, vdev->msix.table_offset, vdev->msix.table_count * MSIX_TABLE_ENTRY_SIZE); in msixtable_access()
A Dvsriov.c135 if (has_msix_cap(vf_vdev) && (bar_idx == vf_vdev->msix.table_bar)) { in create_vf()
136 vf_vdev->msix.mmio_hpa = vf_vbar->base_hpa; in create_vf()
137 vf_vdev->msix.mmio_size = vf_vbar->size; in create_vf()
A Dvmcs9900.c25 struct msix_table_entry *entry = &vdev->msix.table_entries[0]; in trigger_vmcs9900_msix()
75 vdev->msix.mmio_gpa = vbar->base_gpa; in map_vmcs9900_vbar()
A Dvpci.c583 if (vdev->msix.is_vmsix_on_msi) { in write_pt_dev_cfg()
839 if (has_msix_cap(vdev) && (idx == vdev->msix.table_bar)) { in vpci_assign_pcidev()
840 vdev->msix.mmio_hpa = vdev->vbars[idx].base_hpa; in vpci_assign_pcidev()
841 vdev->msix.mmio_size = vdev->vbars[idx].size; in vpci_assign_pcidev()
995 if (vdev->msix.capoff != 0U) { in vpci_vmsix_enabled()
996 msgctrl = pci_vdev_read_vcfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U); in vpci_vmsix_enabled()
A Divshmem.c180 && (vector_index < dest_ivs_dev->pcidev->msix.table_count)) { in ivshmem_server_notify_peer()
182 entry = &(dest_ivs_dev->pcidev->msix.table_entries[vector_index]); in ivshmem_server_notify_peer()
401 vdev->msix.mmio_gpa = vbar->base_gpa; in ivshmem_vbar_map()
/hypervisor/hw/
A Dpci.c790 pdev->msix.capoff = pos; in pci_enumerate_cap()
791 pdev->msix.caplen = MSIX_CAPLEN; in pci_enumerate_cap()
792 len = pdev->msix.caplen; in pci_enumerate_cap()
794 msgctrl = pci_pdev_read_cfg(pdev->bdf, pdev->msix.capoff + PCIR_MSIX_CTRL, 2U); in pci_enumerate_cap()
797 table_info = pci_pdev_read_cfg(pdev->bdf, pdev->msix.capoff + PCIR_MSIX_TABLE, 4U); in pci_enumerate_cap()
799 pdev->msix.table_bar = (uint8_t)(table_info & PCIM_MSIX_BIR_MASK); in pci_enumerate_cap()
801 pdev->msix.table_offset = table_info & ~PCIM_MSIX_BIR_MASK; in pci_enumerate_cap()
802 pdev->msix.table_count = (msgctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U; in pci_enumerate_cap()
804 ASSERT(pdev->msix.table_count <= CONFIG_MAX_MSIX_TABLE_NUM); in pci_enumerate_cap()
808 pdev->msix.cap[idx] = (uint8_t)pci_pdev_read_cfg(pdev->bdf, (uint32_t)pos + idx, 1U); in pci_enumerate_cap()
/hypervisor/include/dm/
A Dvpci.h132 struct pci_msix msix; member
/hypervisor/include/hw/
A Dpci.h303 struct pci_msix_cap msix; member

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