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Searched refs:msr_read (Results 1 – 20 of 20) sorted by relevance

/hypervisor/arch/x86/
A Dlapic.c72 if (msr_read(isr_reg) != 0U) { in clear_lapic_isr()
86 base.value = msr_read(MSR_IA32_APIC_BASE); in early_init_lapic()
121 regs->tpr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TPR); in save_lapic()
122 regs->ppr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_PPR); in save_lapic()
133 (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_TIMER); in save_lapic()
135 (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_LINT0); in save_lapic()
137 (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_LINT1); in save_lapic()
139 (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_ERROR); in save_lapic()
143 (uint32_t) msr_read(MSR_IA32_EXT_APIC_DIV_CONF); in save_lapic()
172 val = msr_read(MSR_IA32_EXT_APIC_SIVR); in suspend_lapic()
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A Dcpu_caps.c123 msr_write(MSR_IA32_MISC_ENABLE, (msr_read(MSR_IA32_MISC_ENABLE) & in disable_host_monitor_wait()
145 uint64_t misc_enable = msr_read(MSR_IA32_MISC_ENABLE); in is_fast_string_erms_supported_and_enabled()
217 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS); in detect_ept_cap()
234 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2); in detect_ept_cap()
247 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS); in detect_apicv_cap()
252 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2); in detect_apicv_cap()
266 msr_val = msr_read(MSR_IA32_VMX_PINBASED_CTLS); in detect_apicv_cap()
279 cpu_caps.vmx_ept_vpid = msr_read(MSR_IA32_VMX_EPT_VPID_CAP); in detect_vmx_mmu_cap()
440 msr_val = msr_read(MSR_IA32_FEATURE_CONTROL); in is_vmx_disabled()
483 vmx_msr = msr_read(msr); in is_vmx_cap_supported()
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A Dsecurity.c70 x86_arch_caps = msr_read(MSR_IA32_ARCH_CAPABILITIES); in disable_rrsba()
75 v = msr_read(MSR_IA32_SPEC_CTRL); in disable_rrsba()
98 x86_arch_capabilities = msr_read(MSR_IA32_ARCH_CAPABILITIES); in check_cpu_security_cap()
279 x86_arch_capabilities = msr_read(MSR_IA32_ARCH_CAPABILITIES); in is_ept_force_4k_ipage()
A Dvmx.c47 tmp32 = (uint32_t)msr_read(MSR_IA32_VMX_BASIC); in vmx_on()
57 tmp64 = msr_read(MSR_IA32_FEATURE_CONTROL); in vmx_on()
A Dcpu.c119 test_ctl = msr_read(MSR_TEST_CTL); in enable_ac_for_splitlock()
132 test_ctl = msr_read(MSR_TEST_CTL); in enable_gp_for_uclock()
648 msr->read_val = msr_read(msr->msr_index); in smpcall_read_msr_func()
658 ret = msr_read(msr_index); in msr_read_pcpu()
A Drdt.c101 pqr_assoc = msr_read(MSR_IA32_PQR_ASSOC); in clos2pqr_msr()
A Dsgx.c112 if ((msr_read(MSR_IA32_FEATURE_CONTROL) & SGX_OPTED_IN) == SGX_OPTED_IN){ in init_sgx()
A Dmmu.c160 tmp64 = msr_read(MSR_IA32_EFER); in enable_paging()
/hypervisor/arch/x86/guest/
A Dvmcs.c57 (msr_read(MSR_IA32_MISC_ENABLE) & (~MSR_IA32_MISC_ENABLE_MONITOR_ENA))); in init_guest_vmx()
59 vcpu_set_guest_msr(vcpu, MSR_IA32_PERF_CTL, msr_read(MSR_IA32_PERF_CTL)); in init_guest_vmx()
168 value64 = msr_read(MSR_IA32_PAT); in init_host_state()
172 value64 = msr_read(MSR_IA32_EFER); in init_host_state()
196 value = msr_read(MSR_IA32_FS_BASE); in init_host_state()
199 value = msr_read(MSR_IA32_GS_BASE); in init_host_state()
214 exec_vmwrite32(VMX_HOST_IA32_SYSENTER_CS, msr_read(ACRN_PSEUDO_PCPUID_MSR)); in init_host_state()
223 vmx_msr = msr_read(msr); in check_vmx_ctrl()
249 vmx_msr = msr_read(msr); in check_vmx_ctrl_64()
567 vmx_rev_id = msr_read(MSR_IA32_VMX_BASIC); in init_vmcs()
A Dnested.c56 msr_val.full = msr_read(msr); in adjust_vmx_ctrls()
100 val64.full = msr_read(MSR_IA32_VMX_MISC); in init_vmx_msrs()
171 msr_value = msr_read(MSR_IA32_VMX_EPT_VPID_CAP); in init_vmx_msrs()
180 msr_value = msr_read(MSR_IA32_VMX_CR0_FIXED0); in init_vmx_msrs()
183 msr_value = msr_read(MSR_IA32_VMX_CR0_FIXED1); in init_vmx_msrs()
186 msr_value = msr_read(MSR_IA32_VMX_CR4_FIXED0); in init_vmx_msrs()
189 msr_value = msr_read(MSR_IA32_VMX_CR4_FIXED1); in init_vmx_msrs()
192 msr_value = msr_read(MSR_IA32_VMX_VMCS_ENUM); in init_vmx_msrs()
695 msr_read(MSR_IA32_VMX_CR0_FIXED1)); in validate_nvmx_cr0()
704 msr_read(MSR_IA32_VMX_CR4_FIXED1)); in validate_nvmx_cr4()
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A Dtrusty.c148 ext_ctx->ia32_star = msr_read(MSR_IA32_STAR); in save_world_ctx()
149 ext_ctx->ia32_lstar = msr_read(MSR_IA32_LSTAR); in save_world_ctx()
150 ext_ctx->ia32_fmask = msr_read(MSR_IA32_FMASK); in save_world_ctx()
151 ext_ctx->ia32_kernel_gs_base = msr_read(MSR_IA32_KERNEL_GS_BASE); in save_world_ctx()
152 ext_ctx->tsc_aux = msr_read(MSR_IA32_TSC_AUX); in save_world_ctx()
A Dvirtual_cr.c445 fixed0 = msr_read(MSR_IA32_VMX_CR0_FIXED0); in init_cr0_cr4_flexible_bits()
446 fixed1 = msr_read(MSR_IA32_VMX_CR0_FIXED1); in init_cr0_cr4_flexible_bits()
474 fixed0 = msr_read(MSR_IA32_VMX_CR4_FIXED0); in init_cr0_cr4_flexible_bits()
475 fixed1 = msr_read(MSR_IA32_VMX_CR4_FIXED1); in init_cr0_cr4_flexible_bits()
A Ducode.c28 val = msr_read(MSR_IA32_BIOS_SIGN_ID); in get_microcode_version()
A Dvmsr.c683 v = msr_read(msr); in rdmsr_vmexit_handler()
715 v = msr_read(msr); in rdmsr_vmexit_handler()
734 v = msr_read(msr); in rdmsr_vmexit_handler()
786 v = msr_read(msr); in rdmsr_vmexit_handler()
835 v = msr_read(msr); in rdmsr_vmexit_handler()
909 if (msr_read(MSR_IA32_TSC_DEADLINE) != 0UL) { in set_tsc_msr_interception()
918 vcpu_set_guest_msr(vcpu, MSR_IA32_TSC_DEADLINE, msr_read(MSR_IA32_TSC_DEADLINE)); in set_tsc_msr_interception()
A Dvcpu.c104 if (val == msr_read(MSR_IA32_EFER)) { in vcpu_set_efer()
930 ectx->ia32_star = msr_read(MSR_IA32_STAR); in context_switch_out()
931 ectx->ia32_cstar = msr_read(MSR_IA32_CSTAR); in context_switch_out()
932 ectx->ia32_lstar = msr_read(MSR_IA32_LSTAR); in context_switch_out()
933 ectx->ia32_fmask = msr_read(MSR_IA32_FMASK); in context_switch_out()
934 ectx->ia32_kernel_gs_base = msr_read(MSR_IA32_KERNEL_GS_BASE); in context_switch_out()
935 ectx->tsc_aux = msr_read(MSR_IA32_TSC_AUX); in context_switch_out()
957 if (vmsr_val != msr_read(MSR_IA32_UMWAIT_CONTROL)) { in context_switch_in()
A Dvmtrr.c112 cap.value = msr_read(MSR_IA32_MTRR_CAP); in init_vmtrr()
124 vmtrr->fixed_range[i].value = msr_read(fixed_mtrr_map[i].msr); in init_vmtrr()
A Dvcat.c362 pvalue = (msr_read(pmsr) & ~get_max_pcbm(vm, res)) | pcbm; in write_vcbm()
A Dvlapic.c376 if (msr_read(MSR_IA32_TSC_DEADLINE) == 0UL) { in vlapic_get_tsc_deadline_msr()
/hypervisor/debug/
A Dprofiling.c117 lvt_perf_ctr = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_PMI); in profiling_enable_pmu()
213 lvt_perf_ctr = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_PMI); in profiling_disable_pmu()
498 = msr_read(my_msr_node->entries[i].msr_id); in profiling_handle_msrops()
506 = msr_read(my_msr_node->entries[i].msr_id); in profiling_handle_msrops()
601 perf_ovf_status = msr_read(MSR_IA32_PERF_GLOBAL_STATUS); in profiling_pmi_handler()
602 lvt_perf_ctr = (uint32_t)msr_read(MSR_IA32_EXT_APIC_LVT_PMI); in profiling_pmi_handler()
649 psample->lsample.lbr_tos = msr_read(MSR_CORE_LASTBRANCH_TOS); in profiling_pmi_handler()
652 = msr_read(MSR_CORE_LASTBRANCH_0_FROM_IP + i); in profiling_pmi_handler()
654 = msr_read(MSR_CORE_LASTBRANCH_0_TO_IP + i); in profiling_pmi_handler()
/hypervisor/include/arch/x86/asm/
A Dcpu.h704 static inline uint64_t msr_read(uint32_t reg_num) in msr_read() function

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