Searched refs:msr_val (Results 1 – 3 of 3) sorted by relevance
212 uint64_t msr_val; in detect_ept_cap() local217 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS); in detect_ept_cap()229 msr_val = msr_val >> 32U; in detect_ept_cap()232 if ((msr_val & VMX_PROCBASED_CTLS_SECONDARY) != 0UL) { in detect_ept_cap()234 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2); in detect_ept_cap()245 uint64_t msr_val; in detect_apicv_cap() local247 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS); in detect_apicv_cap()252 msr_val = msr_read(MSR_IA32_VMX_PROCBASED_CTLS2); in detect_apicv_cap()266 msr_val = msr_read(MSR_IA32_VMX_PINBASED_CTLS); in detect_apicv_cap()436 uint64_t msr_val; in is_vmx_disabled() local[all …]
522 static inline void cpu_msr_write(uint32_t reg, uint64_t msr_val) in cpu_msr_write() argument524 asm volatile (" wrmsr " : : "c" (reg), "a" ((uint32_t)msr_val), "d" ((uint32_t)(msr_val >> 32U))); in cpu_msr_write()
46 union value_64 val64, msr_val; in adjust_vmx_ctrls() local56 msr_val.full = msr_read(msr); in adjust_vmx_ctrls()66 val64.u.lo_32 = msr_val.u.lo_32; in adjust_vmx_ctrls()69 val64.u.hi_32 = msr_val.u.lo_32; in adjust_vmx_ctrls()72 val64.u.hi_32 |= (msr_val.u.hi_32 & request_bits); in adjust_vmx_ctrls()
Completed in 9 milliseconds