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Searched refs:msr_write (Results 1 – 19 of 19) sorted by relevance

/hypervisor/arch/x86/
A Dlapic.c73 msr_write(MSR_IA32_EXT_APIC_EOI, 0U); in clear_lapic_isr()
95 msr_write(MSR_IA32_APIC_BASE, base.value); in early_init_lapic()
98 msr_write(MSR_IA32_APIC_BASE, base.value); in early_init_lapic()
101 msr_write(MSR_IA32_EXT_APIC_SIVR, 0UL); in early_init_lapic()
150 msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, in restore_lapic()
153 msr_write(MSR_IA32_EXT_APIC_LVT_LINT0, in restore_lapic()
155 msr_write(MSR_IA32_EXT_APIC_LVT_LINT1, in restore_lapic()
158 msr_write(MSR_IA32_EXT_APIC_LVT_ERROR, in restore_lapic()
174 msr_write(MSR_IA32_EXT_APIC_SIVR, val); in suspend_lapic()
187 msr_write(MSR_IA32_EXT_APIC_EOI, 0U); in send_lapic_eoi()
[all …]
A Dtsc_deadline_timer.c25 msr_write(MSR_IA32_TSC_DEADLINE, timeout); in set_hw_timeout()
42 msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, val); in init_hw_timer()
48 msr_write(MSR_IA32_TSC_DEADLINE, 0UL); in init_hw_timer()
A Dsecurity.c78 msr_write(MSR_IA32_SPEC_CTRL, v); in disable_rrsba()
157 msr_write(MSR_IA32_FLUSH_CMD, IA32_L1D_FLUSH); in cpu_l1d_flush()
233 msr_write(MSR_IA32_FS_BASE, (uint64_t)psc); in set_fs_base()
A Dpm.c98 msr_write(MSR_IA32_FS_BASE, (uint64_t)psc); in restore_msrs()
175 msr_write(MSR_IA32_TIME_STAMP_COUNTER, per_cpu(tsc_suspend, get_pcpu_id())); in resume_tsc()
298 msr_write(MSR_IA32_PM_ENABLE, 1U); in init_frequency_policy()
333 msr_write(MSR_IA32_HWP_REQUEST, reg); in apply_frequency_policy()
349 msr_write(MSR_IA32_PERF_CTL, pm_s_state_data->px_data[pstate_req].control); in apply_frequency_policy()
A Dcpu.c121 msr_write(MSR_TEST_CTL, test_ctl); in enable_ac_for_splitlock()
134 msr_write(MSR_TEST_CTL, test_ctl); in enable_gp_for_uclock()
525 msr_write(ACRN_PSEUDO_PCPUID_MSR, (uint32_t) pcpu_id); in set_current_pcpu_id()
592 msr_write(MSR_IA32_XSS, xss); in init_pcpu_xsave()
626 msr_write(msr->msr_index, msr->write_val); in smpcall_write_msr_func()
635 msr_write(msr_index, value64); in msr_write_pcpu()
A Dhw_thermal.c37 msr_write(MSR_IA32_EXT_APIC_LVT_THERMAL, val); in init_hw_thermal()
A Dvmx.c64 msr_write(MSR_IA32_FEATURE_CONTROL, tmp64); in vmx_on()
A Drdt.c57 msr_write(info->msr_qos_cfg, 0x1UL); in setup_res_clos_msr()
A Dmmu.c154 msr_write(MSR_IA32_PAT, PAT_POWER_ON_VALUE); in enable_paging()
168 msr_write(MSR_IA32_EFER, tmp64); in enable_paging()
A Dcpu_caps.c123 msr_write(MSR_IA32_MISC_ENABLE, (msr_read(MSR_IA32_MISC_ENABLE) & in disable_host_monitor_wait()
/hypervisor/arch/x86/guest/
A Ducode.c26 msr_write(MSR_IA32_BIOS_SIGN_ID, 0U); in get_microcode_version()
76 msr_write(MSR_IA32_BIOS_UPDT_TRIG, in acrn_update_ucode()
A Dtrusty.c201 msr_write(MSR_IA32_STAR, ext_ctx->ia32_star); in load_world_ctx()
202 msr_write(MSR_IA32_LSTAR, ext_ctx->ia32_lstar); in load_world_ctx()
203 msr_write(MSR_IA32_FMASK, ext_ctx->ia32_fmask); in load_world_ctx()
204 msr_write(MSR_IA32_KERNEL_GS_BASE, ext_ctx->ia32_kernel_gs_base); in load_world_ctx()
205 msr_write(MSR_IA32_TSC_AUX, ext_ctx->tsc_aux); in load_world_ctx()
A Dvcpu.c750 msr_write(MSR_IA32_PRED_CMD, PRED_SET_IBPB); in run_vcpu()
913 msr_write(MSR_IA32_XSS, vcpu_get_guest_msr(vcpu, MSR_IA32_XSS)); in rstore_xsave_area()
948 msr_write(MSR_IA32_STAR, ectx->ia32_star); in context_switch_in()
949 msr_write(MSR_IA32_CSTAR, ectx->ia32_cstar); in context_switch_in()
950 msr_write(MSR_IA32_LSTAR, ectx->ia32_lstar); in context_switch_in()
951 msr_write(MSR_IA32_FMASK, ectx->ia32_fmask); in context_switch_in()
952 msr_write(MSR_IA32_KERNEL_GS_BASE, ectx->ia32_kernel_gs_base); in context_switch_in()
953 msr_write(MSR_IA32_TSC_AUX, ectx->tsc_aux); in context_switch_in()
958 msr_write(MSR_IA32_UMWAIT_CONTROL, vmsr_val); in context_switch_in()
A Dvmsr.c910 msr_write(MSR_IA32_TSC_DEADLINE, vcpu_get_guest_msr(vcpu, MSR_IA32_TSC_DEADLINE)); in set_tsc_msr_interception()
1191 msr_write(msr, v); in wrmsr_vmexit_handler()
1200 msr_write(msr, v); in wrmsr_vmexit_handler()
1210 msr_write(msr, v); in wrmsr_vmexit_handler()
1261 msr_write(msr, v); in wrmsr_vmexit_handler()
1312 msr_write(msr, v); in wrmsr_vmexit_handler()
A Dvcat.c363 msr_write(pmsr, pvalue); in write_vcbm()
A Dvlapic.c411 msr_write(MSR_IA32_TSC_DEADLINE, val); in vlapic_set_tsc_deadline_msr()
413 msr_write(MSR_IA32_TSC_DEADLINE, 0); in vlapic_set_tsc_deadline_msr()
1930 msr_write(MSR_IA32_EXT_APIC_ICR, icr.value); in inject_msi_for_lapic_pt()
2079 msr_write(MSR_IA32_EXT_APIC_ICR, (((uint64_t)papic_id) << 32U) | icr_low); in vlapic_x2apic_pt_icr_access()
/hypervisor/debug/
A Dprofiling.c81 msr_write(msrop->msr_id, msrop->value); in profiling_initialize_pmi()
157 msr_write(msrop->msr_id, msrop->value); in profiling_enable_pmu()
204 msr_write(msrop->msr_id, msrop->value); in profiling_disable_pmu()
514 msr_write(my_msr_node->entries[i].msr_id, in profiling_handle_msrops()
585 msr_write(MSR_IA32_PERF_GLOBAL_CTRL, 0x0U); in profiling_pmi_handler()
595 msr_write(msrop->msr_id, msrop->value); in profiling_pmi_handler()
664 msr_write(MSR_IA32_PERF_GLOBAL_OVF_CTRL, in profiling_pmi_handler()
679 msr_write(msrop->msr_id, msrop->value); in profiling_pmi_handler()
683 msr_write(msrop->msr_id, msrop->value); in profiling_pmi_handler()
704 msr_write(msrop->msr_id, msrop->value); in profiling_pmi_handler()
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/hypervisor/include/arch/x86/asm/
A Dcpu.h709 static inline void msr_write(uint32_t reg_num, uint64_t value64) in msr_write() function
719 msr_write(reg_num, value64); in msr_write_safe()
/hypervisor/common/
A Dtimer.c65 msr_write(MSR_IA32_TSC_DEADLINE, timer->timeout); in update_physical_timer()

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