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/hypervisor/dm/vpci/
A Dvpci_priv.h70 static inline bool msixcap_access(const struct pci_vdev *vdev, uint32_t offset) in msixcap_access() argument
72 return (has_msix_cap(vdev) && in_range(offset, vdev->msix.capoff, vdev->msix.caplen)); in msixcap_access()
78 static inline bool msixtable_access(const struct pci_vdev *vdev, uint32_t offset) in msixtable_access() argument
94 static inline bool sriovcap_access(const struct pci_vdev *vdev, uint32_t offset) in sriovcap_access() argument
96 return (has_sriov_cap(vdev) && in_range(offset, vdev->sriov.capoff, vdev->sriov.caplen)); in sriovcap_access()
102 static inline bool vbar_access(const struct pci_vdev *vdev, uint32_t offset) in vbar_access() argument
104 return is_bar_offset(vdev->nr_bars, offset); in vbar_access()
110 static inline bool cfg_header_access(uint32_t offset) in cfg_header_access() argument
112 return (offset < PCI_CFG_HEADER_LENGTH); in cfg_header_access()
126 static inline bool msicap_access(const struct pci_vdev *vdev, uint32_t offset) in msicap_access() argument
[all …]
A Dvpci_bridge.c90 uint32_t offset, val; in init_vpci_bridge() local
93 for (offset = 0x00U; offset < 0x100U; offset += 4U) { in init_vpci_bridge()
94 val = pci_pdev_read_cfg(vdev->pdev->bdf, offset, 4U); in init_vpci_bridge()
95 pci_vdev_write_vcfg(vdev, offset, 4U, val); in init_vpci_bridge()
157 static int32_t read_vpci_bridge_cfg(struct pci_vdev *vdev, uint32_t offset, in read_vpci_bridge_cfg() argument
160 if ((offset + bytes) <= 0x100U) { in read_vpci_bridge_cfg()
161 *val = pci_vdev_read_vcfg(vdev, offset, bytes); in read_vpci_bridge_cfg()
164 *val = pci_pdev_read_cfg(vdev->pdev->bdf, offset, bytes); in read_vpci_bridge_cfg()
190 static int32_t write_vpci_bridge_cfg(__unused struct pci_vdev *vdev, __unused uint32_t offset, in write_vpci_bridge_cfg() argument
A Dvpci.c127 if (pci_is_valid_access(offset, bytes)) { in vpci_pio_cfgdata_read()
158 if (pci_is_valid_access(offset, bytes)) { in vpci_pio_cfgdata_write()
467 } else if (vbar_access(vdev, offset)) { in read_cfg_header()
509 } else if (vbar_access(vdev, offset)) { in write_cfg_header()
515 if (offset == PCIR_COMMAND) { in write_cfg_header()
547 if (!((offset == PCIR_IO_BASE) && (bytes <= 2)) && (offset != PCIR_IO_LIMIT)) { in write_cfg_header()
565 if (offset == PCIR_INTERRUPT_LINE) { in write_cfg_header()
578 if (cfg_header_access(offset)) { in write_pt_dev_cfg()
580 } else if (msicap_access(vdev, offset)) { in write_pt_dev_cfg()
611 if (cfg_header_access(offset)) { in read_pt_dev_cfg()
[all …]
A Dvdev.c45 val = vdev->cfgdata.data_8[offset]; in pci_vdev_read_vcfg()
48 val = vdev->cfgdata.data_16[offset >> 1U]; in pci_vdev_read_vcfg()
51 val = vdev->cfgdata.data_32[offset >> 2U]; in pci_vdev_read_vcfg()
65 vdev->cfgdata.data_8[offset] = (uint8_t)val; in pci_vdev_write_vcfg()
71 vdev->cfgdata.data_32[offset >> 2U] = val; in pci_vdev_write_vcfg()
107 uint32_t lo, hi, offset; in pci_vdev_update_vbar_base() local
111 offset = pci_bar_offset(idx); in pci_vdev_update_vbar_base()
112 lo = pci_vdev_read_vcfg(vdev, offset, 4U); in pci_vdev_update_vbar_base()
197 uint32_t bar, offset; in pci_vdev_write_vbar() local
212 offset = pci_bar_offset(idx); in pci_vdev_write_vbar()
[all …]
A Dvmsix.c44 void read_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val) in read_vmsix_cap_reg() argument
50 virt = pci_vdev_read_vcfg(vdev, offset, bytes); in read_vmsix_cap_reg()
51 (void)memcpy_s((void *)&pt_mask, bytes, (void *)&msix_pt_mask[offset - vdev->msix.capoff], bytes); in read_vmsix_cap_reg()
53 phy = pci_pdev_read_cfg(vdev->pdev->bdf, offset, bytes); in read_vmsix_cap_reg()
72 bool write_vmsix_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val) in write_vmsix_cap_reg() argument
83 old = pci_vdev_read_vcfg(vdev, offset, bytes); in write_vmsix_cap_reg()
84 pci_vdev_write_vcfg(vdev, offset, bytes, (old & ro_mask) | (val & ~ro_mask)); in write_vmsix_cap_reg()
101 uint64_t offset; in rw_vmsix_table() local
105 offset = mmio->address - vdev->msix.mmio_gpa; in rw_vmsix_table()
106 if (msixtable_access(vdev, (uint32_t)offset)) { in rw_vmsix_table()
[all …]
A Dpci_pt.c326 uint32_t offset; in vdev_bridge_pt_restore_space() local
335 for (offset = PCIR_MEM_BASE; offset < PCIR_IO_BASE_UPPER_16; offset += 4) { in vdev_bridge_pt_restore_space()
401 uint32_t size32, offset, lo, hi = 0U; in init_bars() local
416 offset = sriov_bar_offset(vdev, idx); in init_bars()
419 offset = pci_bar_offset(idx); in init_bars()
421 lo = pci_pdev_read_cfg(pbdf, offset, 4U); in init_bars()
468 offset = sriov_bar_offset(vdev, idx); in init_bars()
470 offset = pci_bar_offset(idx); in init_bars()
608 uint32_t offset; in init_vdev_pt() local
610 for (offset = 0U; offset < PCI_CFG_HEADER_LENGTH; offset += 4U) { in init_vdev_pt()
[all …]
A Dvmcs9900.c36 uint32_t offset, uint32_t bytes, uint32_t * val) in read_vmcs9900_cfg() argument
38 *val = pci_vdev_read_vcfg(vdev, offset, bytes); in read_vmcs9900_cfg()
48 uint16_t offset; in vmcs9900_mmio_handler() local
50 offset = (uint16_t)(mmio->address - vbar->base_gpa); in vmcs9900_mmio_handler()
53 mmio->value = vuart_read_reg(vu, offset); in vmcs9900_mmio_handler()
55 vuart_write_reg(vu, offset, (uint8_t) mmio->value); in vmcs9900_mmio_handler()
97 if (vbar_access(vdev, offset)) { in write_vmcs9900_cfg()
98 vpci_update_one_vbar(vdev, pci_bar_index(offset), val, in write_vmcs9900_cfg()
100 } else if (msixcap_access(vdev, offset)) { in write_vmcs9900_cfg()
101 write_vmsix_cap_reg(vdev, offset, bytes, val); in write_vmcs9900_cfg()
[all …]
A Dvhostbridge.c240 static int32_t read_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset, in read_vhostbridge_cfg() argument
243 *val = pci_vdev_read_vcfg(vdev, offset, bytes); in read_vhostbridge_cfg()
267 static int32_t write_vhostbridge_cfg(struct pci_vdev *vdev, uint32_t offset, in write_vhostbridge_cfg() argument
270 if (!is_bar_offset(PCI_BAR_COUNT, offset)) { in write_vhostbridge_cfg()
271 pci_vdev_write_vcfg(vdev, offset, bytes, val); in write_vhostbridge_cfg()
A Divshmem.c263 (offset < sizeof(ivs_dev->mmio))) { in ivshmem_mmio_handler()
271 if (offset != IVSHMEM_DOORBELL_REG) { in ivshmem_mmio_handler()
272 mmio->value = ivs_dev->mmio.data[offset >> 2U]; in ivshmem_mmio_handler()
277 if (offset != IVSHMEM_IV_POS_REG) { in ivshmem_mmio_handler()
278 if (offset == IVSHMEM_DOORBELL_REG) { in ivshmem_mmio_handler()
283 ivs_dev->mmio.data[offset >> 2U] = mmio->value; in ivshmem_mmio_handler()
314 *val = pci_vdev_read_vcfg(vdev, offset, bytes); in read_ivshmem_vdev_cfg()
433 if (vbar_access(vdev, offset)) { in write_ivshmem_vdev_cfg()
436 } else if (msixcap_access(vdev, offset)) { in write_ivshmem_vdev_cfg()
437 write_vmsix_cap_reg(vdev, offset, bytes, val); in write_ivshmem_vdev_cfg()
[all …]
A Dvpci_mf_dev.c37 static int32_t read_vpci_mf_dev(struct pci_vdev *vdev, uint32_t offset, in read_vpci_mf_dev() argument
40 *val = pci_vdev_read_vcfg(vdev, offset, bytes); in read_vpci_mf_dev()
45 static int32_t write_vpci_mf_dev(__unused struct pci_vdev *vdev, __unused uint32_t offset, in write_vpci_mf_dev() argument
A Dvsriov.c281 void read_sriov_cap_reg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val) in read_sriov_cap_reg() argument
285 *val = pci_pdev_read_cfg(vdev->pdev->bdf, offset, bytes); in read_sriov_cap_reg()
295 void write_sriov_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val) in write_sriov_cap_reg() argument
300 reg = offset - vdev->sriov.capoff; in write_sriov_cap_reg()
313 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
317 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
320 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
333 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
336 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
A Dvmsi.c102 void write_vmsi_cap_reg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val) in write_vmsi_cap_reg() argument
109 (void)memcpy_s((void *)&ro_mask, bytes, (void *)&msi_ro_mask[offset - vdev->msi.capoff], bytes); in write_vmsi_cap_reg()
113 old = pci_vdev_read_vcfg(vdev, offset, bytes); in write_vmsi_cap_reg()
114 pci_vdev_write_vcfg(vdev, offset, bytes, (old & ro_mask) | (val & ~ro_mask)); in write_vmsi_cap_reg()
A Dvroot_port.c79 static int32_t read_vrp_cfg(struct pci_vdev *vdev, uint32_t offset, in read_vrp_cfg() argument
82 *val = pci_vdev_read_vcfg(vdev, offset, bytes); in read_vrp_cfg()
87 static int32_t write_vrp_cfg(__unused struct pci_vdev *vdev, __unused uint32_t offset, in write_vrp_cfg() argument
90 pci_vdev_write_vcfg(vdev, offset, bytes, val); in write_vrp_cfg()
A Dvmsix_on_msi.c129 void write_vmsix_cap_reg_on_msi(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t va… in write_vmsix_cap_reg_on_msi() argument
136 pci_vdev_write_vcfg(vdev, offset, bytes, val); in write_vmsix_cap_reg_on_msi()
140 msi_msgctrl = (uint16_t)pci_pdev_read_cfg(vdev->pdev->bdf, offset, 2U); in write_vmsix_cap_reg_on_msi()
151 pci_pdev_write_cfg(vdev->pdev->bdf, offset, 2U, msi_msgctrl); in write_vmsix_cap_reg_on_msi()
/hypervisor/hw/
A Dpci.c95 addr |= (offset | PCI_CFG_ENABLE); in pio_off_to_address()
104 addr = pio_off_to_address(bdf, offset); in pci_pio_read_cfg()
127 uint32_t addr = pio_off_to_address(bdf, offset); in pci_pio_write_cfg()
147 __unused uint32_t offset, __unused uint32_t bytes) in pci_pio_read_cfg() argument
180 uint32_t addr = mmcfg_off_to_address(bdf, offset); in pci_mmcfg_read_cfg()
196 uint32_t addr = mmcfg_off_to_address(bdf, offset); in pci_mmcfg_write_cfg()
258 pci_pdev_write_cfg(bdf, offset, 4U, ~0U); in get_pci_bar_resource()
546 uint32_t offset, val, msgctrl; in config_pci_bridge() local
554 offset = pdev->msi_capoff + PCIR_MSI_CTRL; in config_pci_bridge()
563 offset = pdev->pcie_capoff + PCIR_PCIE_DEVCAP2; in config_pci_bridge()
[all …]
/hypervisor/include/hw/
A Dpci.h313 uint32_t (*pci_read_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
332 static inline uint32_t pci_bar_index(uint32_t offset) in pci_bar_index() argument
334 return (offset - PCIR_BARS) >> 2U; in pci_bar_index()
337 static inline bool is_bar_offset(uint32_t nr_bars, uint32_t offset) in is_bar_offset() argument
341 if ((offset >= pci_bar_offset(0U)) in is_bar_offset()
342 && (offset < pci_bar_offset(nr_bars))) { in is_bar_offset()
367 uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
403 static inline bool pci_is_valid_access_offset(uint32_t offset, uint32_t bytes) in pci_is_valid_access_offset() argument
405 return ((offset & (bytes - 1U)) == 0U); in pci_is_valid_access_offset()
413 static inline bool pci_is_valid_access(uint32_t offset, uint32_t bytes) in pci_is_valid_access() argument
[all …]
/hypervisor/arch/x86/guest/
A Dvlapic.c571 switch (offset) { in lvt_off_to_idx()
621 switch (offset) { in vlapic_get_lvtptr()
662 switch (offset) { in vlapic_write_lvt()
1355 offset &= ~0x3UL; in vlapic_read()
1356 switch (offset) { in vlapic_read()
2107 (offset != APIC_OFFSET_EOI) && (offset != APIC_OFFSET_SELF_IPI); in apicv_advanced_x2apic_write_msr_may_valid()
2113 uint32_t offset; in vlapic_x2apic_read() local
2148 uint32_t offset; in vlapic_x2apic_write() local
2400 uint32_t offset; in apic_access_vmexit_handler() local
2499 uint32_t offset; in apic_write_vmexit_handler() local
[all …]
A Dvept.c223 uint16_t offset; in get_leaf_entry() local
228 offset = PAGING_ENTRY_OFFSET(gpa, pt_level); in get_leaf_entry()
229 ept_entry = p_ept_entry[offset]; in get_leaf_entry()
402 uint16_t offset; in handle_l2_ept_violation() local
414 offset = PAGING_ENTRY_OFFSET(l2_ept_violation_gpa, pt_level); in handle_l2_ept_violation()
415 guest_ept_entry = p_guest_ept_page[offset]; in handle_l2_ept_violation()
416 shadow_ept_entry = p_shadow_ept_page[offset]; in handle_l2_ept_violation()
439 p_shadow_ept_page[offset] = shadow_ept_entry; in handle_l2_ept_violation()
466 p_shadow_ept_page[offset] = shadow_ept_entry; in handle_l2_ept_violation()
/hypervisor/dm/
A Dvrtc.c397 uint64_t offset; in vrtc_get_current_time() local
537 uint8_t offset; in vrtc_read() local
544 offset = vrtc->addr; in vrtc_read()
547 pio_req->value = offset; in vrtc_read()
550 pio_req->value = cmos_get_reg_val(offset); in vrtc_read()
552 if (offset <= RTC_CENTURY) { in vrtc_read()
556 if(offset == 0xCU) { in vrtc_read()
563 pr_err("vrtc read invalid addr 0x%x", offset); in vrtc_read()
574 return ((offset == RTC_SEC) || (offset == RTC_MIN) || (offset == RTC_HRS) || (offset == RTC_DAY) in vrtc_is_time_register()
575 || (offset == RTC_MONTH) || (offset == RTC_YEAR) || (offset == RTC_CENTURY)); in vrtc_is_time_register()
[all …]
A Dvuart.c427 && (offset == UART16550_THR) && (target_vu != NULL)) { in vuart_write_reg()
436 write_reg(vu, offset, value_u8); in vuart_write_reg()
467 uint16_t offset = offset_arg; in vuart_write() local
472 offset -= vu->port_base; in vuart_write()
473 vuart_write_reg(vu, offset, value_u8); in vuart_write()
530 if (offset == UART16550_DLL) { in vuart_read_reg()
532 } else if (offset == UART16550_DLM) { in vuart_read_reg()
538 switch (offset) { in vuart_read_reg()
602 if (offset == UART16550_RBR) { in vuart_read_reg()
634 uint16_t offset = offset_arg; in vuart_read() local
[all …]
/hypervisor/include/arch/x86/asm/guest/
A Dvlapic.h95 bool (*apic_read_access_may_valid)(uint32_t offset);
96 bool (*apic_write_access_may_valid)(uint32_t offset);
97 bool (*x2apic_read_msr_may_valid)(uint32_t offset);
98 bool (*x2apic_write_msr_may_valid)(uint32_t offset);
/hypervisor/include/dm/
A Dvuart.h120 uint8_t vuart_read_reg(struct acrn_vuart *vu, uint16_t offset);
121 void vuart_write_reg(struct acrn_vuart *vu, uint16_t offset, uint8_t value);
A Dvpci.h108 … int32_t (*write_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
109 … int32_t (*read_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
/hypervisor/arch/x86/
A Dtsc.c97 static inline uint32_t hpet_read(uint32_t offset) in hpet_read() argument
99 return mmio_read32(hpet_hva + offset); in hpet_read()
A Dioapic.c132 ioapic_read_reg32(void *ioapic_base, const uint32_t offset) in ioapic_read_reg32() argument
140 mmio_write32(offset, ioapic_base + IOAPIC_REGSEL); in ioapic_read_reg32()
149 ioapic_write_reg32(void *ioapic_base, const uint32_t offset, const uint32_t value) in ioapic_write_reg32() argument
156 mmio_write32(offset, ioapic_base + IOAPIC_REGSEL); in ioapic_write_reg32()

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