| /hypervisor/dm/vpci/ |
| A D | vmsix_on_msi.c | 151 pci_pdev_write_cfg(vdev->pdev->bdf, offset, 2U, msi_msgctrl); in write_vmsix_cap_reg_on_msi()
154 pci_pdev_write_cfg(vdev->pdev->bdf, get_mask_bits_offset(vdev), 4U, 0xFFFFFFFFU); in write_vmsix_cap_reg_on_msi()
172 pci_pdev_write_cfg(pbdf, get_mask_bits_offset(vdev), 4U, mask_bits); in remap_one_vmsix_entry_on_msi()
187 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR, 0x4U, (uint32_t)info.addr.full); in remap_one_vmsix_entry_on_msi()
189 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR_HIGH, 0x4U, in remap_one_vmsix_entry_on_msi()
191 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA_64BIT, 0x2U, in remap_one_vmsix_entry_on_msi()
194 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA, 0x2U, in remap_one_vmsix_entry_on_msi()
202 pci_pdev_write_cfg(pbdf, get_mask_bits_offset(vdev), 4U, mask_bits); in remap_one_vmsix_entry_on_msi()
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| A D | vmsi.c | 52 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_CTRL, 2U, msgctrl); in enable_disable_msi()
82 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR, 0x4U, (uint32_t)info.addr.full); in remap_vmsi()
84 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR_HIGH, 0x4U, in remap_vmsi()
86 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA_64BIT, 0x2U, (uint16_t)info.data.full); in remap_vmsi()
88 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA, 0x2U, (uint16_t)info.data.full); in remap_vmsi()
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| A D | vsriov.c | 113 pci_pdev_write_cfg(pf_vdev->bdf, pf_vdev->sriov.capoff + PCIR_SRIOV_CONTROL, 2U, control); in create_vf()
313 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
317 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
320 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
333 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
336 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_sriov_cap_reg()
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| A D | pci_pt.c | 81 pci_pdev_write_cfg(vdev->pdev->bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl); in write_pt_vmsix_cap_reg()
331 pci_pdev_write_cfg(pdev->bdf, PCIR_IO_BASE, 2U, pre_val); in vdev_bridge_pt_restore_space()
338 pci_pdev_write_cfg(pdev->bdf, offset, 4U, pre_val); in vdev_bridge_pt_restore_space()
355 pci_pdev_write_cfg(pdev->bdf, PCIR_PRIBUS_1, 2U, pre_val); in vdev_bridge_pt_restore_bus()
361 pci_pdev_write_cfg(pdev->bdf, PCIR_SUBBUS_1, 1U, pre_val); in vdev_bridge_pt_restore_bus()
453 pci_pdev_write_cfg(pbdf, offset, 4U, ~0U); in init_bars()
455 pci_pdev_write_cfg(pbdf, offset, 4U, lo); in init_bars()
472 pci_pdev_write_cfg(pbdf, offset, 4U, ~0U); in init_bars()
474 pci_pdev_write_cfg(pbdf, offset, 4U, hi); in init_bars()
626 pci_pdev_write_cfg(vdev->pdev->bdf, PCIR_COMMAND, 2U, pci_command); in init_vdev_pt()
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| A D | vpci.c | 553 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, value); in write_cfg_header()
595 pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val); in write_pt_dev_cfg()
688 pci_pdev_write_cfg(bdf, offset, bytes, val); in vpci_write_cfg()
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| /hypervisor/hw/ |
| A D | pci.c | 233 void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val) in pci_pdev_write_cfg() function
258 pci_pdev_write_cfg(bdf, offset, 4U, ~0U); in get_pci_bar_resource()
260 pci_pdev_write_cfg(bdf, offset, 4U, res->phy_bar); in get_pci_bar_resource()
277 pci_pdev_write_cfg(pdev->bdf, pci_bar_offset(idx), 4U, pdev->bars[idx].phy_bar); in pdev_restore_bar()
325 pci_pdev_write_cfg(bdf, PCIR_COMMAND, 0x2U, new_cmd); in enable_disable_pci_intx()
550 pci_pdev_write_cfg(pdev->bdf, PCIR_COMMAND, 2U, (uint16_t)val | PCIM_CMD_INTxDIS); in config_pci_bridge()
558 pci_pdev_write_cfg(pdev->bdf, offset, 2U, msgctrl); in config_pci_bridge()
571 pci_pdev_write_cfg(pdev->bdf, offset, 2U, val); in config_pci_bridge()
678 pci_pdev_write_cfg(pdev->bdf, pos + PCIR_PTM_CTRL, 4, ctrl); in pci_enable_ptm_root()
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| /hypervisor/debug/ |
| A D | uart16550.c | 185 pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN); in uart16550_init()
194 pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN); in uart16550_init()
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| /hypervisor/include/hw/ |
| A D | pci.h | 368 void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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