Searched refs:trigger_mode (Results 1 – 9 of 9) sorted by relevance
25 uint32_t trigger_mode:1; member
206 uint64_t trigger_mode:1; member218 uint32_t trigger_mode:1; member
523 uint64_t trigger_mode:1; member
259 irte.bits.remap.trigger_mode = rte.bits.trigger_mode; in ptirq_build_physical_rte()295 rte.bits.trigger_mode = IOAPIC_RTE_TRGRMODE_EDGE; in ptirq_build_physical_rte()298 rte.bits.trigger_mode = IOAPIC_RTE_TRGRMODE_LEVEL; in ptirq_build_physical_rte()479 if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) { in ptirq_handle_intx()696 if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) { in activate_ioapic_rte()
201 rte.bits.trigger_mode = legacy_irq_trigger_mode[irq]; in create_rte_for_legacy_irq()227 rte.bits.trigger_mode = IOAPIC_RTE_TRGRMODE_LEVEL; in create_rte_for_gsi_irq()251 if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) { in ioapic_set_routing()
1334 uint64_t trigger_mode; in dmar_assign_irte() local1340 trigger_mode = 0x0UL; in dmar_assign_irte()1343 trigger_mode = irte->bits.remap.trigger_mode; in dmar_assign_irte()1380 irte->bits.remap.trigger_mode = trigger_mode; in dmar_assign_irte()
110 uint32_t trigger_mode:1; member
69 level = (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL); in vioapic_generate_intr()244 if (is_lapic_pt_configured(vioapic->vm) && (vioapic->rtbl[pin].bits.trigger_mode != 0UL)) { in vioapic_indirect_read()336 if (new.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_EDGE) { in vioapic_indirect_write()
1219 if (entry->pmsi.data.bits.trigger_mode == MSI_DATA_TRGRMODE_LEVEL) { in get_entry_info()1239 if (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL) { in get_entry_info()1362 level = (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL); in get_vioapic_info()1450 (rte.bits.trigger_mode == IOAPIC_RTE_TRGRMODE_LEVEL)? "level" : "edge", in get_ioapic_info()
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