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Searched refs:value (Results 1 – 25 of 61) sorted by relevance

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/hypervisor/include/arch/x86/asm/
A Dio.h24 uint8_t value; in pio_read8() local
26 asm volatile ("inb %1,%0":"=a" (value):"dN"(port)); in pio_read8()
27 return value; in pio_read8()
39 uint16_t value; in pio_read16() local
42 return value; in pio_read16()
54 uint32_t value; in pio_read32() local
57 return value; in pio_read32()
92 *addr64 = value; in mmio_write64()
103 *addr32 = value; in mmio_write32()
114 *addr16 = value; in mmio_write16()
[all …]
A Didt.h24 uint32_t value; member
31 uint32_t value; member
/hypervisor/arch/x86/
A Dvmx.c151 uint64_t value; in exec_vmread64() local
155 : "=a" (value) in exec_vmread64()
159 return value; in exec_vmread64()
164 uint64_t value; in exec_vmread32() local
166 value = exec_vmread64(field); in exec_vmread32()
168 return (uint32_t)value; in exec_vmread32()
173 uint64_t value; in exec_vmread16() local
175 value = exec_vmread64(field); in exec_vmread16()
177 return (uint16_t)value; in exec_vmread16()
184 : : "a" (value), "d"(field_full) in exec_vmwrite64()
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A Dlapic.c45 uint64_t value; member
86 base.value = msr_read(MSR_IA32_APIC_BASE); in early_init_lapic()
95 msr_write(MSR_IA32_APIC_BASE, base.value); in early_init_lapic()
98 msr_write(MSR_IA32_APIC_BASE, base.value); in early_init_lapic()
168 saved_lapic_base_msr.value = msr_read(MSR_IA32_APIC_BASE); in suspend_lapic()
205 icr.value = 0U; in send_startup_ipi()
212 msr_write(MSR_IA32_EXT_APIC_ICR, icr.value); in send_startup_ipi()
231 msr_write(MSR_IA32_EXT_APIC_ICR, icr.value); in send_startup_ipi()
240 msr_write(MSR_IA32_EXT_APIC_ICR, icr.value); in send_startup_ipi()
270 msr_write(MSR_IA32_EXT_APIC_ICR, icr.value); in send_single_ipi()
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/hypervisor/include/arch/x86/asm/lib/
A Dbits.h65 static inline uint16_t fls32(uint32_t value) in fls32() argument
72 : "rm" (value), "i" (INVALID_BIT_INDEX)); in fls32()
76 static inline uint16_t fls64(uint64_t value) in fls64() argument
83 : "rm" (value), "i" (INVALID_BIT_INDEX)); in fls64()
112 static inline uint16_t ffs64(uint64_t value) in ffs64() argument
119 : "rm" (value), "i" (INVALID_BIT_INDEX)); in ffs64()
124 static inline uint16_t ffz64(uint64_t value) in ffz64() argument
126 return ffs64(~value); in ffz64()
163 static inline uint16_t clz(uint32_t value) in clz() argument
165 return ((value != 0U) ? (31U - fls32(value)) : 32U); in clz()
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/hypervisor/dm/
A Dvgpio.c96 uint32_t value, shift; in vgpio_mmio_handler() local
105 value = mmio_read32((const void *)hva); in vgpio_mmio_handler()
111 phys_pin = (value >> shift) & 0xFFU; in vgpio_mmio_handler()
113 value = (value & ~(0xFFU << shift)) | (virt_pin << shift); in vgpio_mmio_handler()
115 mmio->value = (uint64_t)value; in vgpio_mmio_handler()
117 value = (uint32_t)mmio->value; in vgpio_mmio_handler()
119 value = (value & ~(0xFFU << GPIO_MISGCFG_GPDMINTSEL_SHIFT)) | in vgpio_mmio_handler()
122 mmio_write32(value, (void *)hva); in vgpio_mmio_handler()
A Dvrtc.c425 static void cmos_write(uint8_t addr, uint8_t value) in cmos_write() argument
428 pio_write8(value, CMOS_DATA_PORT); in cmos_write()
454 static void cmos_set_reg_val(uint8_t addr, uint8_t value) in cmos_set_reg_val() argument
465 cmos_write(addr, value); in cmos_set_reg_val()
547 pio_req->value = offset; in vrtc_read()
550 pio_req->value = cmos_get_reg_val(offset); in vrtc_read()
557 pio_req->value = vrtc_get_reg_c(vrtc); in vrtc_read()
614 uint32_t value) in vrtc_write() argument
624 vrtc->addr = (uint8_t)(value & 0x7FU); in vrtc_write()
643 vrtc_set_reg_b(vrtc, value); in vrtc_write()
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A Dio_req.c31 req->reqs.mmio_request.value, in acrn_print_request()
41 req->reqs.pio_request.value, in acrn_print_request()
171 uint64_t value; in get_asyncio_desc() local
184 value = io_req->reqs.pio_request.value; in get_asyncio_desc()
190 value = io_req->reqs.mmio_request.value; in get_asyncio_desc()
411 io_req->reqs.pio_request.value = acrn_io_req->reqs.pio_request.value; in complete_ioreq()
415 io_req->reqs.mmio_request.value = acrn_io_req->reqs.mmio_request.value; in complete_ioreq()
552 mmio->value = MMIO_DEFAULT_VALUE_SIZE_1; in mmio_default_access_handler()
555 mmio->value = MMIO_DEFAULT_VALUE_SIZE_2; in mmio_default_access_handler()
558 mmio->value = MMIO_DEFAULT_VALUE_SIZE_4; in mmio_default_access_handler()
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/hypervisor/arch/x86/guest/
A Dvmtrr.c112 cap.value = msr_read(MSR_IA32_MTRR_CAP); in init_vmtrr()
124 vmtrr->fixed_range[i].value = msr_read(fixed_mtrr_map[i].msr); in init_vmtrr()
130 vmtrr->fixed_range[i].value = MTRR_FIXED_RANGE_ALL_WB; in init_vmtrr()
135 vmtrr->fixed_range[i].value); in init_vmtrr()
205 void write_vmtrr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t value) in write_vmtrr() argument
211 if (vmtrr->def_type.value != value) { in write_vmtrr()
212 vmtrr->def_type.value = value; in write_vmtrr()
242 vmtrr->fixed_range[index].value = value; in write_vmtrr()
257 ret = vmtrr->cap.value; in read_vmtrr()
259 ret = vmtrr->def_type.value; in read_vmtrr()
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A Dvmcs.c90 uint64_t value; in init_host_state() local
181 CPU_CR_READ(cr0, &value); in init_host_state()
182 exec_vmwrite(VMX_HOST_CR0, value); in init_host_state()
186 CPU_CR_READ(cr3, &value); in init_host_state()
187 exec_vmwrite(VMX_HOST_CR3, value); in init_host_state()
191 CPU_CR_READ(cr4, &value); in init_host_state()
192 exec_vmwrite(VMX_HOST_CR4, value); in init_host_state()
196 value = msr_read(MSR_IA32_FS_BASE); in init_host_state()
197 exec_vmwrite(VMX_HOST_FS_BASE, value); in init_host_state()
199 value = msr_read(MSR_IA32_GS_BASE); in init_host_state()
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A Dvmx_io.c52 uint64_t value = (uint64_t)pio_req->value; in emulate_pio_complete() local
55 rax = ((rax) & ~mask) | (value & mask); in emulate_pio_complete()
83 pio_req->value = (uint32_t)vcpu_get_gpreg(vcpu, CPU_REG_RAX) & mask; in pio_instr_vmexit_handler()
134 mmio_req->value = 0UL; in ept_violation_vmexit_handler()
A Dassign.c96 intr_src.src.msi.value = entry->phys_sid.msi_id.bdf; in ptirq_free_irte()
137 irte.value.lo_64 = 0UL; in ptirq_build_physical_msi()
138 irte.value.hi_64 = 0UL; in ptirq_build_physical_msi()
147 intr_src.src.msi.value = entry->phys_sid.msi_id.bdf; in ptirq_build_physical_msi()
253 irte.value.lo_64 = 0UL; in ptirq_build_physical_rte()
254 irte.value.hi_64 = 0UL; in ptirq_build_physical_rte()
326 entry->phys_sid.value = phys_sid.value; in add_msix_remapping()
327 entry->virt_sid.value = virt_sid.value; in add_msix_remapping()
389 entry->phys_sid.value = phys_sid.value; in add_intx_remapping()
390 entry->virt_sid.value = virt_sid.value; in add_intx_remapping()
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A Dvm_reset.c31 io_req->reqs.pio_request.value = (VIRTUAL_PM1A_SLP_EN | (5U << 10U)); in triple_fault_shutdown_vm()
82 vcpu->req.reqs.pio_request.value = vm->reset_control; in handle_reset_reg_read()
145 vcpu->req.reqs.pio_request.value = pio_read8(addr); in handle_kb_read()
148 vcpu->req.reqs.pio_request.value = ~0U; in handle_kb_read()
/hypervisor/include/arch/x86/asm/guest/
A Dvmtrr.h22 uint64_t value; member
34 uint64_t value; member
46 uint64_t value; member
64 void write_vmtrr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t value);
/hypervisor/dm/vpci/
A Dvpci.c60 val = cfg_addr->value; in vpci_pio_cfgaddr_read()
63 pio_req->value = val; in vpci_pio_cfgaddr_read()
124 cfg_addr.value = atomic_readandclear32(&vpci->addr.value); in vpci_pio_cfgdata_read()
128 bdf.value = cfg_addr.bits.bdf; in vpci_pio_cfgdata_read()
133 pio_req->value = val; in vpci_pio_cfgdata_read()
155 cfg_addr.value = atomic_readandclear32(&vpci->addr.value); in vpci_pio_cfgdata_write()
200 mmio->value = val; in vpci_mmio_cfg_access()
548 uint32_t value = val; in write_cfg_header() local
726 vdev->bdf.value = dev_config->vbdf.value; in vpci_init_vdev()
808 bdf.value = pcidev->phys_bdf; in vpci_assign_pcidev()
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A Dvmsix.c117 (void)memcpy_s(&mmio->value, (size_t)mmio->size, in rw_vmsix_table()
121 &mmio->value, (size_t)mmio->size); in rw_vmsix_table()
131 mmio->value = mmio_read(hva, mmio->size); in rw_vmsix_table()
133 mmio_write(hva, mmio->size, mmio->value); in rw_vmsix_table()
138 mmio->value = 0UL; in rw_vmsix_table()
A Dvmsix_on_msi.c33 if (pdev->bdf.value == vmsix_on_msi_devs[i].bdf.value) { in need_vmsix_on_msi_emulation()
57 intr_src.src.msi.value = pdev->bdf.value; in reserve_vmsix_on_msi_irtes()
179 ret = ptirq_prepare_msix_remap(vpci2vm(vdev->vpci), vdev->bdf.value, pbdf.value, in remap_one_vmsix_entry_on_msi()
A Dvmsi.c81 if (ptirq_prepare_msix_remap(vm, vdev->bdf.value, pbdf.value, 0U, &info, INVALID_IRTE_ID) == 0) { in remap_vmsi()
130 ptirq_remove_msix_remapping(vpci2vm(vdev->vpci), vdev->pdev->bdf.value, 1U); in deinit_vmsi()
/hypervisor/arch/x86/configs/
A Dpci_dev.c91 dev_config->vbdf.value = pdev->bdf.value; in init_one_dev_config()
92 dev_config->pbdf.value = pdev->bdf.value; in init_one_dev_config()
/hypervisor/debug/
A Duart16550.c42 .bdf.value = CONFIG_SERIAL_PCI_BDF,
130 uint64_t value; in early_pgtable_map_uart() local
132 CPU_CR_READ(cr3, &value); in early_pgtable_map_uart()
135 pml4e = pml4e_offset((uint64_t *)value, addr); in early_pgtable_map_uart()
286 uart.bdf.value = 0U; in uart16550_set_property()
291 uart.bdf.value = data; in uart16550_set_property()
303 if (uart.enabled && (uart.bdf.value != 0)) { in is_pci_dbg_uart()
304 if (bdf_value.value == uart.bdf.value) { in is_pci_dbg_uart()
A Dnpk_log.c52 static inline int32_t npk_write(const char *value, void *addr, size_t sz) in npk_write() argument
57 mmio_write64(*(uint64_t *)value, addr); in npk_write()
60 mmio_write32(*(uint32_t *)value, addr); in npk_write()
63 mmio_write16(*(uint16_t *)value, addr); in npk_write()
66 mmio_write8(*(uint8_t *)value, addr); in npk_write()
/hypervisor/scripts/
A Dgenld.sh13 value=${arr[1]}
14 sed -i "s/\b$field\b/$value/g" $out
/hypervisor/lib/
A Dsprintf.c242 param->emit(PRINT_CMD_COPY, param->vars.value, in format_number()
298 param->vars.value = pos; in print_pow2()
303 param->vars.value = NULL; in print_pow2()
308 static void print_decimal(struct print_param *param, int64_t value) in print_decimal() argument
320 v.qword = ((uint64_t)value) & param->vars.mask; in print_decimal()
326 if (((param->vars.flags & PRINT_FLAG_UINT32) == 0U) && (value < 0)) { in print_decimal()
327 v.qword = (uint64_t)-value; in print_decimal()
366 param->vars.value = pos; in print_decimal()
371 param->vars.value = NULL; in print_decimal()
/hypervisor/include/lib/
A Dutil.h35 static inline bool mem_aligned_check(uint64_t value, uint64_t req_align) in mem_aligned_check() argument
37 return ((value & (req_align - 1UL)) == 0UL); in mem_aligned_check()
/hypervisor/common/
A Dptdev.c54 return hash64(sid->value + (uint64_t)vm, PTIRQ_ENTRY_HASHBITS); in ptirq_hash_key()
75 if ((intr_type == n->intr_type) && (sid->value == n->phys_sid.value)) { in find_ptirq_entry()
86 if ((intr_type == n->intr_type) && (sid->value == n->virt_sid.value) && (vm == n->vm)) { in find_ptirq_entry()

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