1 /*
2  * Copyright (C) 2021-2022 Intel Corporation.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING!
8  */
9 
10 #ifndef PLATFORM_ACPI_INFO_H
11 #define PLATFORM_ACPI_INFO_H
12 
13 /*
14  * BIOS Information
15  * Vendor: American Megatrends International, LLC.
16  * Version: E5000XXU3F00105-BPCIe
17  * Release Date: 08/25/2021
18  * BIOS Revision: 5.19
19  *
20  * Base Board Information
21  * Manufacturer: Default string
22  * Product Name: Default string
23  * Version: Default string
24  */
25 
26 /* pm sstate data */
27 #define PM1A_EVT_ADDRESS        0x1800UL
28 #define PM1A_EVT_ACCESS_SIZE    0x2U
29 #define PM1A_CNT_ADDRESS        0x1804UL
30 
31 #define WAKE_VECTOR_32          0x3F6A400CUL
32 #define WAKE_VECTOR_64          0x3F6A4018UL
33 
34 #define RESET_REGISTER_ADDRESS  0xCF9UL
35 #define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
36 #define RESET_REGISTER_VALUE    0x6U
37 
38 /* DRHD of DMAR */
39 #define DRHD_COUNT              2U
40 
41 #define DRHD0_DEV_CNT           0x1U
42 #define DRHD0_SEGMENT           0x0U
43 #define DRHD0_FLAGS             0x0U
44 #define DRHD0_REG_BASE          0xFED90000UL
45 #define DRHD0_IGNORE            true
46 #define DRHD0_DEVSCOPE0_TYPE    0x1U
47 #define DRHD0_DEVSCOPE0_ID      0x0U
48 #define DRHD0_DEVSCOPE0_BUS     0x0U
49 #define DRHD0_DEVSCOPE0_PATH    0x10U
50 
51 #define DRHD1_DEV_CNT           0x2U
52 #define DRHD1_SEGMENT           0x0U
53 #define DRHD1_FLAGS             0x1U
54 #define DRHD1_REG_BASE          0xFED91000UL
55 #define DRHD1_IGNORE            false
56 #define DRHD1_DEVSCOPE0_TYPE    0x3U
57 #define DRHD1_DEVSCOPE0_ID      0x2U
58 #define DRHD1_DEVSCOPE0_BUS     0x0U
59 #define DRHD1_DEVSCOPE0_PATH    0xf7U
60 #define DRHD1_DEVSCOPE1_TYPE    0x4U
61 #define DRHD1_DEVSCOPE1_ID      0x0U
62 #define DRHD1_DEVSCOPE1_BUS     0x0U
63 #define DRHD1_DEVSCOPE1_PATH    0xf6U
64 
65 /* PCI mmcfg base of MCFG */
66 #define DEFAULT_PCI_MMCFG_BASE   0xc0000000UL
67 
68 /* PCI mmcfg bus number of MCFG */
69 #define DEFAULT_PCI_MMCFG_START_BUS 	 0x0U
70 #define DEFAULT_PCI_MMCFG_END_BUS   	 0xFFU
71 
72 
73 #endif /* PLATFORM_ACPI_INFO_H */
74