1 /*
2  * Copyright (C) 2021-2022 Intel Corporation.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /*
8  * BIOS Information
9  * Vendor: American Megatrends International, LLC.
10  * Version: E5000XXU3F00105-BPCIe
11  * Release Date: 08/25/2021
12  * BIOS Revision: 5.19
13  *
14  * Base Board Information
15  * Manufacturer: Default string
16  * Product Name: Default string
17  * Version: Default string
18  */
19 
20 #include <asm/board.h>
21 #include <asm/vtd.h>
22 #include <asm/msr.h>
23 #include <asm/rdt.h>
24 #include <pci.h>
25 #include <misc_cfg.h>
26 
27 static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
28 	{
29 		.type   = DRHD0_DEVSCOPE0_TYPE,
30 		.id     = DRHD0_DEVSCOPE0_ID,
31 		.bus    = DRHD0_DEVSCOPE0_BUS,
32 		.devfun = DRHD0_DEVSCOPE0_PATH,
33 	},
34 };
35 
36 static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
37 	{
38 		.type   = DRHD1_DEVSCOPE0_TYPE,
39 		.id     = DRHD1_DEVSCOPE0_ID,
40 		.bus    = DRHD1_DEVSCOPE0_BUS,
41 		.devfun = DRHD1_DEVSCOPE0_PATH,
42 	},
43 	{
44 		.type   = DRHD1_DEVSCOPE1_TYPE,
45 		.id     = DRHD1_DEVSCOPE1_ID,
46 		.bus    = DRHD1_DEVSCOPE1_BUS,
47 		.devfun = DRHD1_DEVSCOPE1_PATH,
48 	},
49 };
50 
51 static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
52 	{
53 		.dev_cnt       = DRHD0_DEV_CNT,
54 		.segment       = DRHD0_SEGMENT,
55 		.flags         = DRHD0_FLAGS,
56 		.reg_base_addr = DRHD0_REG_BASE,
57 		.ignore        = DRHD0_IGNORE,
58 		.devices       = drhd0_dev_scope
59 	},
60 	{
61 		.dev_cnt       = DRHD1_DEV_CNT,
62 		.segment       = DRHD1_SEGMENT,
63 		.flags         = DRHD1_FLAGS,
64 		.reg_base_addr = DRHD1_REG_BASE,
65 		.ignore        = DRHD1_IGNORE,
66 		.devices       = drhd1_dev_scope
67 	},
68 };
69 
70 struct dmar_info plat_dmar_info = {
71 	.drhd_count = DRHD_COUNT,
72 	.drhd_units = drhd_info_array,
73 };
74 
75 #ifdef CONFIG_RDT_ENABLED
76 union clos_config platform_l2_clos_array_0[8] = {
77 };
78 
79 union clos_config platform_l2_clos_array_1[8] = {
80 };
81 
82 union clos_config platform_l2_clos_array_2[8] = {
83 };
84 
85 union clos_config platform_l2_clos_array_3[8] = {
86 };
87 
88 union clos_config platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
89 union clos_config platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
90 struct rdt_ins rdt_ins_l2[4] = {
91 	{
92 		.res.cache = {
93 			.bitmask = 0xfffff,
94 			.cbm_len = 20,
95 			.is_cdp_enabled = false,
96 		},
97 		.num_closids = 8,
98 		.num_clos_config = 0,
99 		.clos_config_array = platform_l2_clos_array_0,
100 		.cpu_mask = 0x1,
101 	},
102 	{
103 		.res.cache = {
104 			.bitmask = 0xfffff,
105 			.cbm_len = 20,
106 			.is_cdp_enabled = false,
107 		},
108 		.num_closids = 8,
109 		.num_clos_config = 0,
110 		.clos_config_array = platform_l2_clos_array_1,
111 		.cpu_mask = 0x2,
112 	},
113 	{
114 		.res.cache = {
115 			.bitmask = 0xfffff,
116 			.cbm_len = 20,
117 			.is_cdp_enabled = false,
118 		},
119 		.num_closids = 8,
120 		.num_clos_config = 0,
121 		.clos_config_array = platform_l2_clos_array_2,
122 		.cpu_mask = 0x4,
123 	},
124 	{
125 		.res.cache = {
126 			.bitmask = 0xfffff,
127 			.cbm_len = 20,
128 			.is_cdp_enabled = false,
129 		},
130 		.num_closids = 8,
131 		.num_clos_config = 0,
132 		.clos_config_array = platform_l2_clos_array_3,
133 		.cpu_mask = 0x8,
134 	},
135 };
136 
137 struct rdt_type res_cap_info[RDT_NUM_RESOURCES] = {
138 	{
139 		.res_id = RDT_RESID_L2,
140 		.msr_qos_cfg = MSR_IA32_L2_QOS_CFG,
141 		.msr_base = MSR_IA32_L2_MASK_BASE,
142 		.num_ins = 4,
143 		.ins_array = rdt_ins_l2,
144 	},
145 };
146 
147 #endif
148 
149 static const struct acrn_cstate_data board_cpu_cx[1] = {
150 	{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x00U, 0x00U},	/* C1 */
151 };
152 
153 /* Px data is not available */
154 static const struct acrn_pstate_data board_cpu_px[0];
155 
156 const struct cpu_state_table board_cpu_state_tbl = {
157 	"11th Gen Intel(R) Core(TM) i7-1185GRE @ 2.80GHz",
158 	{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,
159 	(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
160 };
161 const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
162 
163 const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM];
164 
165 struct acrn_cpufreq_limits cpufreq_limits[MAX_PCPU_NUM] = {
166 	{
167 		.guaranteed_hwp_lvl = 255,
168 		.highest_hwp_lvl = 255,
169 		.lowest_hwp_lvl = 1,
170 		.nominal_pstate = 0,
171 		.performance_pstate = 0,
172 	},
173 	{
174 		.guaranteed_hwp_lvl = 255,
175 		.highest_hwp_lvl = 255,
176 		.lowest_hwp_lvl = 1,
177 		.nominal_pstate = 0,
178 		.performance_pstate = 0,
179 	},
180 	{
181 		.guaranteed_hwp_lvl = 255,
182 		.highest_hwp_lvl = 255,
183 		.lowest_hwp_lvl = 1,
184 		.nominal_pstate = 0,
185 		.performance_pstate = 0,
186 	},
187 	{
188 		.guaranteed_hwp_lvl = 255,
189 		.highest_hwp_lvl = 255,
190 		.lowest_hwp_lvl = 1,
191 		.nominal_pstate = 0,
192 		.performance_pstate = 0,
193 	},
194 };
195