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Searched refs:ASSERT (Results 1 – 25 of 34) sorted by relevance

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/hypervisor/acpi_parser/
A Ddmar_parse.c120 ASSERT(dev_count <= MAX_DRHD_DEVSCOPES, "parsed dev_count > MAX_DRHD_DEVSCOPES"); in handle_one_drhd()
170 ASSERT(dmar_tbl != NULL, ""); in parse_dmar_table()
178 ASSERT(dmar_header->length >= sizeof(struct acpi_dmar_header), "corrupted DMAR table"); in parse_dmar_table()
183 ASSERT(acpi_drhd->address != 0UL, "a zero base address DRHD. Please fix the BIOS."); in parse_dmar_table()
209 ASSERT(dmar_unit_cnt <= MAX_DRHDS, "parsed dmar_unit_cnt > MAX_DRHDS"); in parse_dmar_table()
/hypervisor/arch/x86/
A Drtcm.c84 ASSERT((rtcm_binary->address != 0UL && rtcm_binary->size != 0U), in parse_rtct()
99 ASSERT((rtcm_binary->address != 0UL && rtcm_binary->size != 0U), in parse_rtct()
152 ASSERT(((header->magic == RTCM_MAGIC_PTCM) || (header->magic == RTCM_MAGIC_RTCM)), in init_software_sram()
162 ASSERT(rtcm_ret_code == 0); in init_software_sram()
A Dpage.c45 ASSERT(page != NULL, "no page aviable!"); in alloc_page()
A Dirq.c228 ASSERT(irq_static_mappings[idx].irq == 0U, ""); in init_irq_descs_arch()
229 ASSERT(irq_static_mappings[idx].vector == 0U, ""); in init_irq_descs_arch()
A Dnotify.c125 ASSERT(vcpu_index < CONFIG_MAX_VM_NUM, ""); in handle_pi_notification()
A Drdt.c70 ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res); in setup_res_clos_msr()
A Dpm.c351 ASSERT(false, "invalid p-state index"); in apply_frequency_policy()
A De820.c112 ASSERT(hv_e820_entries_nr <= E820_MAX_ENTRIES, "e820 entry overflow"); in insert_e820_entry()
/hypervisor/include/debug/
A Dlogmsg.h35 #define ASSERT(x, ...) \ macro
44 #define ASSERT(x, ...) do { } while (0) macro
/hypervisor/lib/
A Dstack_protector.c12 ASSERT(false, "stack check fails in HV\n"); in __stack_chk_fail()
/hypervisor/common/
A Defi_mmap.c42 ASSERT((uefi_info->memmap_size / uefi_info->memdesc_size) <= MAX_EFI_MMAP_ENTRIES); in init_efi_mmap_entries()
A Devent.c40 ASSERT((event->waiting_thread == NULL), "only support exclusive waiting"); in wait_event()
A Dsched_prio.c21 ASSERT(ctl->pcpu_id == get_pcpu_id(), "Init scheduler on wrong CPU!"); in sched_prio_init()
A Dsched_iorr.c134 ASSERT(get_pcpu_id() == ctl->pcpu_id, "Init scheduler on wrong CPU!"); in sched_iorr_init()
A Dtimer.c104 ASSERT(list_empty(&timer->node), "add timer again!\n"); in add_timer()
A Dsched_bvt.c185 ASSERT(ctl->pcpu_id == get_pcpu_id(), "Init scheduler on wrong CPU!"); in sched_bvt_init()
/hypervisor/arch/x86/guest/
A Dvirtual_cr.c438 ASSERT(((CR0_PASSTHRU_BITS ^ CR0_TRAP_AND_PASSTHRU_BITS) ^ CR0_TRAP_AND_EMULATE_BITS) == in init_cr0_cr4_flexible_bits()
441 ASSERT(((CR4_PASSTHRU_BITS ^ CR4_TRAP_AND_PASSTHRU_BITS) ^ CR4_TRAP_AND_EMULATE_BITS) == in init_cr0_cr4_flexible_bits()
575 ASSERT((idx <= 15U), "index out of range"); in cr_access_vmexit_handler()
589 ASSERT(false, "Unhandled CR access"); in cr_access_vmexit_handler()
A Dvept.c173 ASSERT(desc != NULL, "Get vept_desc failed!"); in get_vept_desc()
270 ASSERT(guest_ept_level == IA32E_PT, "Only support 4K page for guest EPT!"); in generate_shadow_ept_entry()
405 ASSERT(desc != NULL, "Invalid shadow EPTP!"); in handle_l2_ept_violation()
A Dpm.c63 ASSERT((pm_state_info->px_cnt <= MAX_PSTATE), "failed to setup cpu px"); in vm_setup_cpu_px()
80 ASSERT((pm_state_info->cx_cnt <= MAX_CX_ENTRY), "failed to setup cpu cx"); in vm_setup_cpu_cx()
A Dvmsr.c392 ASSERT(cfg->pclosids != NULL, "error, cfg->pclosids is NULL"); in prepare_auto_msr_area()
412 ASSERT(vcpu->arch.msr_area.count <= MSR_AREA_COUNT, "error, please check MSR_AREA_COUNT!"); in prepare_auto_msr_area()
478 ASSERT(false, "invalid CAT msr address"); in cat_msr_to_index_of_emulated_msr()
A Dve820.c122 ASSERT(entries_count <= E820_MAX_ENTRIES, "e820 entry overflow"); in filter_mem_from_service_vm_e820()
A Dvm.c305 ASSERT(service_vm_ptr != NULL, "service_vm_ptr is NULL"); in get_service_vm()
438 ASSERT((base & PAGE_MASK) != 0U, "%02x:%02x.%d bar[%d] 0x%lx, is not 4K aligned!", in deny_pci_bar_access()
1136 ASSERT(false, "%s: Wrong VM (VM id: %u) configuration, can't set both REE and TEE flags", in launch_vms()
/hypervisor/hw/
A Dpci.c183 ASSERT(pci_is_valid_access(offset, bytes), "the offset should be aligned with 2/4 byte\n"); in pci_mmcfg_read_cfg()
199 ASSERT(pci_is_valid_access(offset, bytes), "the offset should be aligned with 2/4 byte\n"); in pci_mmcfg_write_cfg()
491 ASSERT(bdfs_from_drhds->pci_bdf_map_count < BDF_MAPPING_NUM, in pci_add_bdf_from_drhd()
804 ASSERT(pdev->msix.table_count <= CONFIG_MAX_MSIX_TABLE_NUM); in pci_enumerate_cap()
/hypervisor/dm/vpci/
A Dvmsix.c59 ASSERT(vdev->msix.table_count <= (PAGE_SIZE/ MSIX_TABLE_ENTRY_SIZE), ""); in read_vmsix_cap_reg()
A Dvsriov.c163 ASSERT(is_vf_enabled(pf_vdev), "VF_ENABLE was not set successfully on the hardware"); in enable_vfs()

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