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Searched refs:DMAR_GSTS_REG (Results 1 – 2 of 2) sorted by relevance

/hypervisor/arch/x86/
A Dvtd.c371 dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_IRES, 0U, &status); in dmar_enable_intr_remapping()
373 status = iommu_read32(dmar_unit, DMAR_GSTS_REG); in dmar_enable_intr_remapping()
390 dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_TES, 0U, &status); in dmar_enable_translation()
392 status = iommu_read32(dmar_unit, DMAR_GSTS_REG); in dmar_enable_translation()
410 dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_IRES, DMA_GSTS_IRES, &status); in dmar_disable_intr_remapping()
425 dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_TES, DMA_GSTS_TES, &status); in dmar_disable_translation()
449 dmar_unit->gcmd = iommu_read32(dmar_unit, DMAR_GSTS_REG) & 0x96FFFFFFU; // Reset the one-shot bits; in dmar_register_hrhd()
683 dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_IRTPS, 0U, &status); in dmar_set_intr_remap_table()
723 dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_RTPS, 0U, &status); in dmar_set_root_table()
902 dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_QIES, 0U, &status); in dmar_enable_qi()
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/hypervisor/include/arch/x86/asm/
A Dvtd.h24 #define DMAR_GSTS_REG 0x1cU /* Global status register */ macro

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