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Searched refs:bits (Results 1 – 25 of 38) sorted by relevance

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/hypervisor/arch/x86/guest/
A Dassign.c139 irte.bits.remap.vector = vector; in ptirq_build_physical_msi()
142 irte.bits.remap.rh = MSI_ADDR_RH; in ptirq_build_physical_msi()
143 irte.bits.remap.dest = dest_mask; in ptirq_build_physical_msi()
246 vector = rte.bits.vector; in ptirq_build_physical_rte()
255 irte.bits.remap.vector = vector; in ptirq_build_physical_rte()
258 irte.bits.remap.dest = dest_mask; in ptirq_build_physical_rte()
259 irte.bits.remap.trigger_mode = rte.bits.trigger_mode; in ptirq_build_physical_rte()
275 rte.bits.intr_mask = 1; in ptirq_build_physical_rte()
280 rte.bits.vector = vector; in ptirq_build_physical_rte()
672 vbdf.bits.b, vbdf.bits.d, vbdf.bits.f, entry_nr, entry->vmsi.data.bits.vector, in ptirq_prepare_msix_remap()
[all …]
A Dvmtrr.c79 return (vmtrr->def_type.bits.enable != 0U); in is_mtrr_enabled()
84 return ((vmtrr->cap.bits.fix != 0U) && in is_fixed_range_mtrr_enabled()
85 (vmtrr->def_type.bits.fixed_enable != 0U)); in is_fixed_range_mtrr_enabled()
90 return (uint8_t)(vmtrr->def_type.bits.type); in get_default_memory_type()
105 vmtrr->cap.bits.vcnt = 0U; in init_vmtrr()
106 vmtrr->cap.bits.fix = 1U; in init_vmtrr()
107 vmtrr->def_type.bits.enable = 1U; in init_vmtrr()
108 vmtrr->def_type.bits.fixed_enable = 1U; in init_vmtrr()
109 vmtrr->def_type.bits.type = MTRR_MEM_TYPE_UC; in init_vmtrr()
116 if (cap.bits.fix != 0U) { in init_vmtrr()
A Dvlapic.c1853 if (address.bits.addr_base == MSI_ADDR_BASE) { in inject_msi_for_non_lapic_pt()
1865 dest = address.bits.dest_field; in inject_msi_for_non_lapic_pt()
1867 rh = (address.bits.rh == MSI_ADDR_RH); in inject_msi_for_non_lapic_pt()
1869 delmode = (uint32_t)(data.bits.delivery_mode); in inject_msi_for_non_lapic_pt()
1870 vec = (uint32_t)(data.bits.vector); in inject_msi_for_non_lapic_pt()
1905 if (vmsi_addr.bits.addr_base == MSI_ADDR_BASE) { in inject_msi_for_lapic_pt()
1906 vdest = vmsi_addr.bits.dest_field; in inject_msi_for_lapic_pt()
1925 icr.bits.dest_field = dest; in inject_msi_for_lapic_pt()
1926 icr.bits.vector = vmsi_data.bits.vector; in inject_msi_for_lapic_pt()
1927 icr.bits.delivery_mode = vmsi_data.bits.delivery_mode; in inject_msi_for_lapic_pt()
[all …]
/hypervisor/dm/
A Dvioapic.c68 delmode = rte.bits.delivery_mode; in vioapic_generate_intr()
78 vector = rte.bits.vector; in vioapic_generate_intr()
79 dest = rte.bits.dest_field; in vioapic_generate_intr()
258 vioapic->rtbl[pin].bits.remote_irr = phys_rte.bits.remote_irr; in vioapic_indirect_read()
337 new.bits.remote_irr = 0U; in vioapic_indirect_write()
368 …if ((new.bits.intr_mask == IOAPIC_RTE_MASK_CLR) || (last.bits.intr_mask == IOAPIC_RTE_MASK_CLR)) { in vioapic_indirect_write()
451 if ((rte.bits.vector != vector) || in vioapic_process_eoi()
452 (rte.bits.remote_irr == 0U)) { in vioapic_process_eoi()
466 if ((rte.bits.vector != vector) || in vioapic_process_eoi()
467 (rte.bits.remote_irr == 0U)) { in vioapic_process_eoi()
[all …]
/hypervisor/dm/vpci/
A Dvdev.c148 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx, in pci_vdev_update_vbar_base()
164 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx, base, in pci_vdev_update_vbar_base()
184 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx, in check_pt_dev_pio_bars()
207 bar |= (vbar->bar_type.bits & (~PCI_BASE_ADDRESS_IO_MASK)); in pci_vdev_write_vbar()
209 bar |= (vbar->bar_type.bits & (~PCI_BASE_ADDRESS_MEM_MASK)); in pci_vdev_write_vbar()
A Dvsriov.c115 pf_vdev->bdf.bits.b, pf_vdev->bdf.bits.d, pf_vdev->bdf.bits.f); in create_vf()
228 pf_vdev->bdf.bits.b, pf_vdev->bdf.bits.d, pf_vdev->bdf.bits.f); in enable_vfs()
A Dvmcs9900.c31 vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, entry->addr, entry->data); in trigger_vmcs9900_msix()
132 mmio_vbar->bar_type.bits = PCIM_BAR_MEM_32; in init_vmcs9900()
138 msix_vbar->bar_type.bits = PCIM_BAR_MEM_32; in init_vmcs9900()
A Dvpci.c89 vbdf.value = cfg_addr->bits.bdf; in vpci_pio_cfgaddr_write()
125 if (cfg_addr.bits.enable != 0U) { in vpci_pio_cfgdata_read()
126 uint32_t offset = (uint16_t)cfg_addr.bits.reg_num + (addr - PCI_CONFIG_DATA); in vpci_pio_cfgdata_read()
128 bdf.value = cfg_addr.bits.bdf; in vpci_pio_cfgdata_read()
156 if (cfg_addr.bits.enable != 0U) { in vpci_pio_cfgdata_write()
157 uint32_t offset = (uint16_t)cfg_addr.bits.reg_num + (addr - PCI_CONFIG_DATA); in vpci_pio_cfgdata_write()
159 bdf.value = cfg_addr.bits.bdf; in vpci_pio_cfgdata_write()
315 ret = move_pt_device(NULL, vm->iommu, (uint8_t)vdev->pdev->bdf.bits.b, in assign_vdev_pt_iommu_domain()
332 ret = move_pt_device(vm->iommu, NULL, (uint8_t)vdev->pdev->bdf.bits.b, in remove_vdev_pt_iommu_domain()
691 bdf.bits.b, bdf.bits.d, bdf.bits.f, offset, val); in vpci_write_cfg()
[all …]
A Dpci_pt.c422 vbar->bar_type.bits = lo; in init_bars()
437 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx, lo, in init_bars()
458 vbar->bar_type.bits &= (uint32_t)(~mask); in init_bars()
566 …Hide sriov cap for %02x:%02x.%x", vdev->pdev->bdf.bits.b, vdev->pdev->bdf.bits.d, vdev->pdev->bdf.… in vdev_pt_hide_sriov_cap()
A Divshmem.c478 vbar->bar_type.bits = addr; in init_ivshmem_bar()
480 vbar->bar_type.bits &= (~mask); in init_ivshmem_bar()
489 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f); in init_ivshmem_bar()
556 PCIM_HDRTYPE_NORMAL | ((vdev->bdf.bits.f == 0U) ? PCIM_MFDEV : 0U)); in init_ivshmem_vdev()
A Dvmsix_on_msi.c113 vdev->vbars[i].bar_type.bits = PCIM_BAR_MEM_32; in init_vmsix_on_msi()
185 info.addr.ir_bits.intr_index_high = ir_index.bits.index_high; in remap_one_vmsix_entry_on_msi()
186 info.addr.ir_bits.intr_index_low = ir_index.bits.index_low; in remap_one_vmsix_entry_on_msi()
/hypervisor/hw/
A Dpci.c352 pr_info("hv owned dev: (%x:%x:%x)", pbdf.bits.b, pbdf.bits.d, pbdf.bits.f); in is_hv_owned_pdev()
445 pbdf.bits.d = dev; in scan_pci_hierarchy()
446 pbdf.bits.f = 0U; in scan_pci_hierarchy()
607 __func__, pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f, cnt); in init_all_dev_config()
683 pdev->bdf.bits.b, pdev->bdf.bits.d, in pci_enable_ptm_root()
690 pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enable_ptm_root()
731 pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enumerate_ext_cap()
743 pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enumerate_ext_cap()
756 pdev->bdf.bits.b, pdev->bdf.bits.d, pdev->bdf.bits.f, pos); in pci_enumerate_ext_cap()
766 pdev->bdf.bits.d, pdev->bdf.bits.f); in pci_enumerate_ext_cap()
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/hypervisor/arch/x86/
A Dioapic.c200 rte.bits.intr_mask = IOAPIC_RTE_MASK_SET; in create_rte_for_legacy_irq()
202 rte.bits.dest_mode = DEFAULT_DEST_MODE; in create_rte_for_legacy_irq()
203 rte.bits.delivery_mode = DEFAULT_DELIVERY_MODE; in create_rte_for_legacy_irq()
204 rte.bits.vector = vr; in create_rte_for_legacy_irq()
207 rte.bits.intr_polarity = IOAPIC_RTE_INTPOL_AHI; in create_rte_for_legacy_irq()
210 rte.bits.dest_field = 1U; in create_rte_for_legacy_irq()
226 rte.bits.intr_mask = IOAPIC_RTE_MASK_SET; in create_rte_for_gsi_irq()
228 rte.bits.dest_mode = DEFAULT_DEST_MODE; in create_rte_for_gsi_irq()
230 rte.bits.vector = vr; in create_rte_for_gsi_irq()
342 rte.bits.intr_mask = IOAPIC_RTE_MASK_SET; in ioapic_irq_gsi_mask_unmask()
[all …]
A Dvtd.c806 dmar_bdf.bits.b, dmar_bdf.bits.d, dmar_bdf.bits.f, low); in fault_record_analysis()
994 pr_err("no dmar unit found for device: %x:%x.%x", sid.bits.b, sid.bits.d, sid.bits.f); in is_dmar_unit_valid()
996 dev_dbg(DBG_LEVEL_IOMMU, "device is ignored : %x:%x.%x", sid.bits.b, sid.bits.d, sid.bits.f); in is_dmar_unit_valid()
1056 pr_err("already present for %x:%x.%x", bus, sid.bits.d, sid.bits.f); in iommu_attach_device()
1324 __func__, sid.bits.b, sid.bits.d, sid.bits.f, num, intr_src->is_msi, *start_id); in dmar_reserve_irte()
1364 irte_pi.bits.post.vector = irte->bits.remap.vector; in dmar_assign_irte()
1366 irte_pi.bits.post.svt = 0x1UL; in dmar_assign_irte()
1369 irte_pi.bits.post.mode = 0x1UL; in dmar_assign_irte()
1377 irte->bits.remap.svt = 0x1UL; in dmar_assign_irte()
1378 irte->bits.remap.sid = sid.value; in dmar_assign_irte()
[all …]
A Dlapic.c209 icr.bits.destination_mode = INTR_LAPIC_ICR_PHYSICAL; in send_startup_ipi()
210 icr.bits.shorthand = INTR_LAPIC_ICR_USE_DEST_ARRAY; in send_startup_ipi()
211 icr.bits.delivery_mode = INTR_LAPIC_ICR_INIT; in send_startup_ipi()
228 icr.bits.shorthand = INTR_LAPIC_ICR_USE_DEST_ARRAY; in send_startup_ipi()
229 icr.bits.delivery_mode = INTR_LAPIC_ICR_STARTUP; in send_startup_ipi()
230 icr.bits.vector = (uint8_t)(cpu_startup_start_address >> 12U); in send_startup_ipi()
A Dcpu_caps.c46 uint32_t bits; member
478 static bool is_vmx_cap_supported(uint32_t msr, uint32_t bits) in is_vmx_cap_supported() argument
489 return (((vmx_msr_high & bits) == bits) && ((vmx_msr_low & bits) == 0U)); in is_vmx_cap_supported()
507 if (!is_vmx_cap_supported(vmx_caps[i].msr, vmx_caps[i].bits)) { in check_essential_vmx_caps()
509 vmx_caps[i].msr, msr_read(vmx_caps[i].msr), vmx_caps[i].bits); in check_essential_vmx_caps()
/hypervisor/acpi_parser/
A Ddmar_parse.c45 dmar_bdf.bits.b = busno; in dmar_path_bdf()
46 dmar_bdf.bits.d = path->device; in dmar_path_bdf()
47 dmar_bdf.bits.f = path->function; in dmar_path_bdf()
50 dmar_bdf.bits.b = get_secondary_bus(dmar_bdf.bits.b, dmar_bdf.bits.d, dmar_bdf.bits.f); in dmar_path_bdf()
51 dmar_bdf.bits.d = path[i].device; in dmar_path_bdf()
52 dmar_bdf.bits.f = path[i].function; in dmar_path_bdf()
/hypervisor/include/lib/
A Dhash.h25 static inline uint64_t hash64(uint64_t key, uint32_t bits) in hash64() argument
27 return (key * HASH_FACTOR64) >> (64U - bits); in hash64()
/hypervisor/include/arch/x86/asm/
A Didt.h28 } bits; member
42 } bits; member
A Dlapic.h30 } bits; member
/hypervisor/include/arch/x86/asm/guest/
A Dvmtrr.h30 } bits; member
42 } bits; member
/hypervisor/debug/
A Dshell.c1218 *dest = entry->pmsi.addr.bits.dest_field; in get_entry_info()
1238 *dest = rte.bits.dest_field; in get_entry_info()
1299 pgsi, vgsi, bdf.bits.b, bdf.bits.d, bdf.bits.f, in get_ptdev_info()
1300 vbdf.bits.b, vbdf.bits.d, vbdf.bits.f); in get_ptdev_info()
1358 mask = (rte.bits.intr_mask == IOAPIC_RTE_MASK_SET); in get_vioapic_info()
1361 delmode = rte.bits.delivery_mode; in get_vioapic_info()
1363 vector = rte.bits.vector; in get_vioapic_info()
1364 dest = rte.bits.dest_field; in get_vioapic_info()
1448 rte.bits.vector, rte.bits.dest_field, in get_ioapic_info()
1451 rte.bits.delivery_mode, rte.bits.remote_irr, in get_ioapic_info()
[all …]
/hypervisor/include/common/
A Dptdev.h41 } bits __packed;
81 } bits __packed;
112 } bits __packed;
/hypervisor/include/arch/x86/asm/lib/
A Dbits.h293 static inline uint16_t bitmap_weight(uint64_t bits) in bitmap_weight() argument
295 return (uint16_t)__builtin_popcountl(bits); in bitmap_weight()
/hypervisor/arch/x86/configs/
A Dpci_dev.c82 && (pdev->bdf.bits.f == 0U)) in init_one_dev_config()

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