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Searched refs:msgctrl (Results 1 – 7 of 7) sorted by relevance

/hypervisor/dm/vpci/
A Dvmsi.c45 uint32_t msgctrl = pci_pdev_read_cfg(pbdf, capoff + PCIR_MSI_CTRL, 2U); in enable_disable_msi() local
48 msgctrl |= PCIM_MSICTRL_MSI_ENABLE; in enable_disable_msi()
50 msgctrl &= ~PCIM_MSICTRL_MSI_ENABLE; in enable_disable_msi()
52 pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_CTRL, 2U, msgctrl); in enable_disable_msi()
107 uint32_t msgctrl, old, ro_mask = ~0U; in write_vmsi_cap_reg() local
116 msgctrl = pci_vdev_read_vcfg(vdev, vdev->msi.capoff + PCIR_MSI_CTRL, 2U); in write_vmsi_cap_reg()
117 if ((msgctrl & (PCIM_MSICTRL_MSI_ENABLE | PCIM_MSICTRL_MME_MASK)) == PCIM_MSICTRL_MSI_ENABLE) { in write_vmsi_cap_reg()
A Dvmsix_on_msi.c29 uint16_t msgctrl; in need_vmsix_on_msi_emulation() local
35 msgctrl = (uint16_t)pci_pdev_read_cfg(pdev->bdf, pdev->msi_capoff + PCIR_MSI_CTRL, 2U); in need_vmsix_on_msi_emulation()
36 *vector_count = 1U << ((msgctrl & PCIM_MSICTRL_MMC_MASK) >> 1U); in need_vmsix_on_msi_emulation()
37 if ((*vector_count > 1U) && ((msgctrl & PER_VECTOR_MASK_CAP) != 0U)) { in need_vmsix_on_msi_emulation()
131 uint16_t old_msgctrl, msgctrl; in write_vmsix_cap_reg_on_msi() local
137 msgctrl = (uint16_t)pci_vdev_read_vcfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U); in write_vmsix_cap_reg_on_msi()
139 if (((old_msgctrl ^ msgctrl) & (PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK)) != 0U) { in write_vmsix_cap_reg_on_msi()
146 if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) { in write_vmsix_cap_reg_on_msi()
153 if ((msgctrl & PCIM_MSIXCTRL_FUNCTION_MASK) != 0U) { in write_vmsix_cap_reg_on_msi()
A Dpci_pt.c73 uint32_t msgctrl; in write_pt_vmsix_cap_reg() local
76 msgctrl = pci_vdev_read_vcfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U); in write_pt_vmsix_cap_reg()
78 if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) { in write_pt_vmsix_cap_reg()
81 pci_pdev_write_cfg(vdev->pdev->bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl); in write_pt_vmsix_cap_reg()
A Dvmsix.c184 msixcap.msgctrl = (uint16_t)entry_num - 1U; in add_vmsix_capability()
A Dvpci.c992 uint32_t msgctrl; in vpci_vmsix_enabled() local
996 msgctrl = pci_vdev_read_vcfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U); in vpci_vmsix_enabled()
997 if (((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) && in vpci_vmsix_enabled()
998 ((msgctrl & PCIM_MSIXCTRL_FUNCTION_MASK) == 0U)) { in vpci_vmsix_enabled()
/hypervisor/hw/
A Dpci.c546 uint32_t offset, val, msgctrl; in config_pci_bridge() local
556 msgctrl = pci_pdev_read_cfg(pdev->bdf, offset, 2U); in config_pci_bridge()
557 msgctrl &= ~PCIM_MSICTRL_MSI_ENABLE; in config_pci_bridge()
558 pci_pdev_write_cfg(pdev->bdf, offset, 2U, msgctrl); in config_pci_bridge()
776 uint32_t msgctrl; in pci_enumerate_cap() local
794 msgctrl = pci_pdev_read_cfg(pdev->bdf, pdev->msix.capoff + PCIR_MSIX_CTRL, 2U); in pci_enumerate_cap()
802 pdev->msix.table_count = (msgctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U; in pci_enumerate_cap()
/hypervisor/include/dm/
A Dvpci.h67 uint16_t msgctrl; member

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