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Searched refs:pci_vdev_write_vcfg (Results 1 – 14 of 14) sorted by relevance

/hypervisor/dm/vpci/
A Dvhostbridge.c135 pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0xbU); in init_vhostbridge()
145 pci_vdev_write_vcfg(vdev, 0x48U, 4U, 0xfed10001U); in init_vhostbridge()
148 pci_vdev_write_vcfg(vdev, 0x50U, 4U, 0x000002c1U); in init_vhostbridge()
150 pci_vdev_write_vcfg(vdev, 0x54U, 4U, 0x00000033U); in init_vhostbridge()
152 pci_vdev_write_vcfg(vdev, 0x58U, 4U, 0x7ff00007U); in init_vhostbridge()
154 pci_vdev_write_vcfg(vdev, 0xa8U, 4U, 0x80000000U); in init_vhostbridge()
156 pci_vdev_write_vcfg(vdev, 0xacU, 4U, 0x00000002U); in init_vhostbridge()
158 pci_vdev_write_vcfg(vdev, 0xb0U, 4U, 0x7c000001U); in init_vhostbridge()
160 pci_vdev_write_vcfg(vdev, 0xb4U, 4U, 0x7b800001U); in init_vhostbridge()
162 pci_vdev_write_vcfg(vdev, 0xb8U, 4U, 0x7b000001U); in init_vhostbridge()
[all …]
A Dvroot_port.c22 pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, VRP_VENDOR); in init_vrp()
23 pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, VRP_DEVICE); in init_vrp()
26 pci_vdev_write_vcfg(vdev, PCIR_STATUS, 2U, PCIM_STATUS_CAPPRESENT); in init_vrp()
29 pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0x01U); in init_vrp()
32 pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_PCI); in init_vrp()
35 pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE); in init_vrp()
38 pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, PCIM_HDRTYPE_BRIDGE); in init_vrp()
41 pci_vdev_write_vcfg(vdev, PCIR_CAP_PTR, 1U, PCIE_CAP_VPOS); in init_vrp()
59 pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCIR_PCIE_DEVCAP, 4U, in init_vrp()
66 pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCIR_PCIE_DEVCTRL, 2U, in init_vrp()
[all …]
A Dvpci_bridge.c95 pci_vdev_write_vcfg(vdev, offset, 4U, val); in init_vpci_bridge()
99 pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, 0x8086U); in init_vpci_bridge()
100 pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, 0x9d12U); in init_vpci_bridge()
102 pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0xf1U); in init_vpci_bridge()
104 pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, (PCIM_HDRTYPE_BRIDGE | PCIM_MFDEV)); in init_vpci_bridge()
105 pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE); in init_vpci_bridge()
106 pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_PCI); in init_vpci_bridge()
A Dvpci_mf_dev.c21 pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, PCI_DUMMY_DEVICE_VENDOR); in init_vpci_mf_dev()
22 pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, PCI_DUMMY_DEVICE_ID); in init_vpci_mf_dev()
23 pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, DUMMY_MF_REV); in init_vpci_mf_dev()
24 pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, DUMMY_MF_CLASS); in init_vpci_mf_dev()
25 pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, PCIM_HDRTYPE_NORMAL | PCIM_MFDEV); in init_vpci_mf_dev()
A Dvmcs9900.c103 pci_vdev_write_vcfg(vdev, offset, bytes, val); in write_vmcs9900_cfg()
118 pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, MCS9900_VENDOR); in init_vmcs9900()
119 pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, MCS9900_DEV); in init_vmcs9900()
120 pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_SIMPLECOMM); in init_vmcs9900()
121 pci_vdev_write_vcfg(vdev, PCIV_SUB_SYSTEM_ID, 2U, 0x1000U); in init_vmcs9900()
122 pci_vdev_write_vcfg(vdev, PCIV_SUB_VENDOR_ID, 2U, 0xa000U); in init_vmcs9900()
123 pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, 0x0U); in init_vmcs9900()
124 pci_vdev_write_vcfg(vdev, PCIR_CLASS_CODE, 1U, 0x2U); in init_vmcs9900()
A Dvmsix_on_msi.c101 pci_vdev_write_vcfg(vdev, vdev->msix.capoff, 1U, 0x11U); in init_vmsix_on_msi()
103 pci_vdev_write_vcfg(vdev, vdev->msix.capoff + 2U, 2U, pdev->irte_count - 1U); in init_vmsix_on_msi()
105 pci_vdev_write_vcfg(vdev, vdev->msix.capoff + 4U, 4U, i); in init_vmsix_on_msi()
107 pci_vdev_write_vcfg(vdev, vdev->msix.capoff + 8U, 4U, 2048U + i); in init_vmsix_on_msi()
136 pci_vdev_write_vcfg(vdev, offset, bytes, val); in write_vmsix_cap_reg_on_msi()
A Divshmem.c439 pci_vdev_write_vcfg(vdev, offset, bytes, val); in write_ivshmem_vdev_cfg()
551 pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, IVSHMEM_VENDOR_ID); in init_ivshmem_vdev()
552 pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, IVSHMEM_DEVICE_ID); in init_ivshmem_vdev()
553 pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, IVSHMEM_REV); in init_ivshmem_vdev()
554 pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, IVSHMEM_CLASS); in init_ivshmem_vdev()
555 pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, in init_ivshmem_vdev()
558 pci_vdev_write_vcfg(vdev, PCIV_SUB_VENDOR_ID, 2U, IVSHMEM_INTEL_SUBVENDOR_ID); in init_ivshmem_vdev()
560 pci_vdev_write_vcfg(vdev, PCIV_SUB_SYSTEM_ID, 2U, region->region_id); in init_ivshmem_vdev()
A Dvmsi.c114 pci_vdev_write_vcfg(vdev, offset, bytes, (old & ro_mask) | (val & ~ro_mask)); in write_vmsi_cap_reg()
153 pci_vdev_write_vcfg(vdev, vdev->msi.capoff, 4U, val); in init_vmsi()
A Dpci_pt.c563 pci_vdev_write_vcfg(vdev, pre_pos, 4U, vhdr); in vdev_pt_hide_sriov_cap()
587 …pci_vdev_write_vcfg(vdev, PCIR_ASLS_CTL, 4U, gpu_opregion_gpa | (gpu_asls_phys & ~PCIM_ASLS_OPREGI… in passthru_gpu_opregion()
611 pci_vdev_write_vcfg(vdev, offset, 4U, pci_pdev_read_cfg(vdev->pdev->bdf, offset, 4U)); in init_vdev_pt()
619 …pci_vdev_write_vcfg(vdev, PCIR_ASLS_CTL, 4U, pci_pdev_read_cfg(vdev->pdev->bdf, PCIR_ASLS_CTL, 4U)… in init_vdev_pt()
642 pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, vid); in init_vdev_pt()
643 pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, did); in init_vdev_pt()
A Dvpci.c556 pci_vdev_write_vcfg(vdev, offset, bytes, val); in write_cfg_header()
566 pci_vdev_write_vcfg(vdev, offset, bytes, (val & 0xfU)); in write_cfg_header()
833 pci_vdev_write_vcfg(vdev, PCIR_INTERRUPT_LINE, 1U, pcidev->intr_line); in vpci_assign_pcidev()
834 pci_vdev_write_vcfg(vdev, PCIR_INTERRUPT_PIN, 1U, pcidev->intr_pin); in vpci_assign_pcidev()
970 pci_vdev_write_vcfg(vdev, PCIR_CAP_PTR, 1U, capoff); in vpci_add_capability()
971 pci_vdev_write_vcfg(vdev, PCIR_STATUS, 2U, sts|PCIM_STATUS_CAPPRESENT); in vpci_add_capability()
973 pci_vdev_write_vcfg(vdev, vdev->prev_capoff + 1U, 1U, capoff); in vpci_add_capability()
980 pci_vdev_write_vcfg(vdev, capoff + 1U, 1U, 0U); in vpci_add_capability()
A Dvdev.c61 void pci_vdev_write_vcfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val) in pci_vdev_write_vcfg() function
213 pci_vdev_write_vcfg(vdev, offset, 4U, bar); in pci_vdev_write_vbar()
A Dvmsix.c84 pci_vdev_write_vcfg(vdev, offset, bytes, (old & ro_mask) | (val & ~ro_mask)); in write_vmsix_cap_reg()
A Dvpci_priv.h175 void pci_vdev_write_vcfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
A Dvsriov.c145 pci_vdev_write_vcfg(vf_vdev, pci_bar_offset(bar_idx), 4U, 0U); in create_vf()

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